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drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order
Starting with TGL the disabling order of HDMI transcoder clock vs. DDI BUF has swapped, fix this. There hasn't been any issues seen related to this, but let's follow the spec. Reported-by: Sandeep K Lakkakula <sandeep.k.lakkakula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220617112807.1586621-1-imre.deak@intel.com
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@ -2691,10 +2691,14 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
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dig_port->set_infoframes(encoder, false,
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old_crtc_state, old_conn_state);
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intel_ddi_disable_pipe_clock(old_crtc_state);
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if (DISPLAY_VER(dev_priv) < 12)
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intel_ddi_disable_pipe_clock(old_crtc_state);
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intel_disable_ddi_buf(encoder, old_crtc_state);
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if (DISPLAY_VER(dev_priv) >= 12)
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intel_ddi_disable_pipe_clock(old_crtc_state);
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intel_display_power_put(dev_priv,
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dig_port->ddi_io_power_domain,
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fetch_and_zero(&dig_port->ddi_io_wakeref));
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