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Merge branch 'remotes/lorenzo/pci/uniphier'
- Add DT binding and endpoint driver support for UniPhier NX1 SoC (Kunihiko Hayashi) * remotes/lorenzo/pci/uniphier: PCI: uniphier-ep: Add NX1 support PCI: uniphier-ep: Add SoC data structure dt-bindings: PCI: uniphier-ep: Add bindings for NX1 SoC
This commit is contained in:
Bjorn Helgaas
commit
c1e10d81da
2 changed files with 138 additions and 26 deletions
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@ -20,7 +20,9 @@ allOf:
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properties:
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compatible:
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const: socionext,uniphier-pro5-pcie-ep
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enum:
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- socionext,uniphier-pro5-pcie-ep
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- socionext,uniphier-nx1-pcie-ep
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reg:
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minItems: 4
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@ -41,20 +43,26 @@ properties:
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- const: atu
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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items:
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- const: gio
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- const: link
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oneOf:
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- items: # for Pro5
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- const: gio
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- const: link
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- const: link # for NX1
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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items:
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- const: gio
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- const: link
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oneOf:
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- items: # for Pro5
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- const: gio
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- const: link
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- const: link # for NX1
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num-ib-windows:
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const: 16
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@ -10,6 +10,7 @@
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/of_device.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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@ -31,6 +32,17 @@
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#define PCL_RSTCTRL2 0x0024
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#define PCL_RSTCTRL_PHY_RESET BIT(0)
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#define PCL_PINCTRL0 0x002c
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#define PCL_PERST_PLDN_REGEN BIT(12)
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#define PCL_PERST_NOE_REGEN BIT(11)
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#define PCL_PERST_OUT_REGEN BIT(8)
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#define PCL_PERST_PLDN_REGVAL BIT(4)
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#define PCL_PERST_NOE_REGVAL BIT(3)
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#define PCL_PERST_OUT_REGVAL BIT(0)
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#define PCL_PIPEMON 0x0044
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#define PCL_PCLK_ALIVE BIT(15)
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#define PCL_MODE 0x8000
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#define PCL_MODE_REGEN BIT(8)
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#define PCL_MODE_REGVAL BIT(0)
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@ -51,6 +63,9 @@
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#define PCL_APP_INTX 0x8074
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#define PCL_APP_INTX_SYS_INT BIT(0)
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#define PCL_APP_PM0 0x8078
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#define PCL_SYS_AUX_PWR_DET BIT(8)
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/* assertion time of INTx in usec */
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#define PCL_INTX_WIDTH_USEC 30
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@ -60,7 +75,14 @@ struct uniphier_pcie_ep_priv {
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struct clk *clk, *clk_gio;
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struct reset_control *rst, *rst_gio;
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struct phy *phy;
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const struct pci_epc_features *features;
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const struct uniphier_pcie_ep_soc_data *data;
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};
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struct uniphier_pcie_ep_soc_data {
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bool has_gio;
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void (*init)(struct uniphier_pcie_ep_priv *priv);
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int (*wait)(struct uniphier_pcie_ep_priv *priv);
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const struct pci_epc_features features;
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};
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#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
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@ -91,7 +113,7 @@ static void uniphier_pcie_phy_reset(struct uniphier_pcie_ep_priv *priv,
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writel(val, priv->base + PCL_RSTCTRL2);
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}
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static void uniphier_pcie_init_ep(struct uniphier_pcie_ep_priv *priv)
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static void uniphier_pcie_pro5_init_ep(struct uniphier_pcie_ep_priv *priv)
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{
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u32 val;
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@ -116,6 +138,55 @@ static void uniphier_pcie_init_ep(struct uniphier_pcie_ep_priv *priv)
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msleep(100);
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}
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static void uniphier_pcie_nx1_init_ep(struct uniphier_pcie_ep_priv *priv)
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{
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u32 val;
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/* set EP mode */
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val = readl(priv->base + PCL_MODE);
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val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
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writel(val, priv->base + PCL_MODE);
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/* use auxiliary power detection */
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val = readl(priv->base + PCL_APP_PM0);
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val |= PCL_SYS_AUX_PWR_DET;
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writel(val, priv->base + PCL_APP_PM0);
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/* assert PERST# */
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val = readl(priv->base + PCL_PINCTRL0);
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val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
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| PCL_PERST_PLDN_REGVAL);
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val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
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| PCL_PERST_PLDN_REGEN;
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writel(val, priv->base + PCL_PINCTRL0);
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uniphier_pcie_ltssm_enable(priv, false);
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usleep_range(100000, 200000);
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/* deassert PERST# */
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val = readl(priv->base + PCL_PINCTRL0);
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val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
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writel(val, priv->base + PCL_PINCTRL0);
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}
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static int uniphier_pcie_nx1_wait_ep(struct uniphier_pcie_ep_priv *priv)
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{
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u32 status;
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int ret;
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/* wait PIPE clock */
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ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
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status & PCL_PCLK_ALIVE, 100000, 1000000);
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if (ret) {
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dev_err(priv->pci.dev,
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"Failed to initialize controller in EP mode\n");
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return ret;
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}
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return 0;
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}
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static int uniphier_pcie_start_link(struct dw_pcie *pci)
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{
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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@ -209,7 +280,7 @@ uniphier_pcie_get_features(struct dw_pcie_ep *ep)
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct uniphier_pcie_ep_priv *priv = to_uniphier_pcie(pci);
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return priv->features;
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return &priv->data->features;
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}
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static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
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@ -238,7 +309,8 @@ static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)
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if (ret)
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goto out_rst_assert;
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uniphier_pcie_init_ep(priv);
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if (priv->data->init)
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priv->data->init(priv);
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uniphier_pcie_phy_reset(priv, true);
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@ -248,8 +320,16 @@ static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)
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uniphier_pcie_phy_reset(priv, false);
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if (priv->data->wait) {
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ret = priv->data->wait(priv);
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if (ret)
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goto out_phy_exit;
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}
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return 0;
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out_phy_exit:
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phy_exit(priv->phy);
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out_rst_gio_assert:
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reset_control_assert(priv->rst_gio);
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out_rst_assert:
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@ -277,8 +357,8 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
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if (!priv)
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return -ENOMEM;
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priv->features = of_device_get_match_data(dev);
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if (WARN_ON(!priv->features))
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priv->data = of_device_get_match_data(dev);
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if (WARN_ON(!priv->data))
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return -EINVAL;
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priv->pci.dev = dev;
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@ -288,13 +368,15 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->clk_gio = devm_clk_get(dev, "gio");
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if (IS_ERR(priv->clk_gio))
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return PTR_ERR(priv->clk_gio);
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if (priv->data->has_gio) {
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priv->clk_gio = devm_clk_get(dev, "gio");
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if (IS_ERR(priv->clk_gio))
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return PTR_ERR(priv->clk_gio);
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priv->rst_gio = devm_reset_control_get_shared(dev, "gio");
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if (IS_ERR(priv->rst_gio))
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return PTR_ERR(priv->rst_gio);
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priv->rst_gio = devm_reset_control_get_shared(dev, "gio");
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if (IS_ERR(priv->rst_gio))
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return PTR_ERR(priv->rst_gio);
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}
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priv->clk = devm_clk_get(dev, "link");
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if (IS_ERR(priv->clk))
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@ -321,13 +403,31 @@ static int uniphier_pcie_ep_probe(struct platform_device *pdev)
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return dw_pcie_ep_init(&priv->pci.ep);
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}
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static const struct pci_epc_features uniphier_pro5_data = {
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.linkup_notifier = false,
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.msi_capable = true,
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.msix_capable = false,
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.align = 1 << 16,
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.bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
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.reserved_bar = BIT(BAR_4),
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static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
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.has_gio = true,
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.init = uniphier_pcie_pro5_init_ep,
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.wait = NULL,
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.features = {
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.linkup_notifier = false,
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.msi_capable = true,
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.msix_capable = false,
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.align = 1 << 16,
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.bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
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.reserved_bar = BIT(BAR_4),
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},
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};
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static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {
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.has_gio = false,
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.init = uniphier_pcie_nx1_init_ep,
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.wait = uniphier_pcie_nx1_wait_ep,
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.features = {
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.linkup_notifier = false,
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.msi_capable = true,
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.msix_capable = false,
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.align = 1 << 12,
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.bar_fixed_64bit = BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4),
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},
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};
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static const struct of_device_id uniphier_pcie_ep_match[] = {
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@ -335,6 +435,10 @@ static const struct of_device_id uniphier_pcie_ep_match[] = {
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.compatible = "socionext,uniphier-pro5-pcie-ep",
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.data = &uniphier_pro5_data,
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},
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{
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.compatible = "socionext,uniphier-nx1-pcie-ep",
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.data = &uniphier_nx1_data,
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},
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{ /* sentinel */ },
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};
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