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ASoC: amd: acp: add i2s clock generation support for acp6.3 based platforms
Add I2S LRCLK & BCLK generation code for ACP6.3 based platforms. Signed-off-by: Syed Saba Kareem <Syed.SabaKareem@amd.com> Link: https://lore.kernel.org/r/20231021145110.478744-3-Syed.SabaKareem@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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1 changed files with 16 additions and 3 deletions
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@ -27,14 +27,19 @@
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#define DRV_NAME "acp_i2s_playcap"
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#define I2S_MASTER_MODE_ENABLE 1
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#define I2S_MODE_ENABLE 0
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#define I2S_FORMAT_MODE GENMASK(1, 1)
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#define LRCLK_DIV_FIELD GENMASK(10, 2)
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#define BCLK_DIV_FIELD GENMASK(23, 11)
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#define ACP63_LRCLK_DIV_FIELD GENMASK(12, 2)
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#define ACP63_BCLK_DIV_FIELD GENMASK(23, 13)
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static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
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{
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u32 i2s_clk_reg, val;
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struct acp_chip_info *chip;
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struct device *dev;
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dev = adata->dev;
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chip = dev_get_platdata(dev);
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switch (dai_id) {
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case I2S_SP_INSTANCE:
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i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN;
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@ -52,8 +57,16 @@ static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
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val = I2S_MASTER_MODE_ENABLE;
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val |= I2S_MODE_ENABLE & BIT(1);
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val |= FIELD_PREP(LRCLK_DIV_FIELD, adata->lrclk_div);
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val |= FIELD_PREP(BCLK_DIV_FIELD, adata->bclk_div);
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switch (chip->acp_rev) {
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case ACP63_DEV:
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val |= FIELD_PREP(ACP63_LRCLK_DIV_FIELD, adata->lrclk_div);
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val |= FIELD_PREP(ACP63_BCLK_DIV_FIELD, adata->bclk_div);
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break;
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default:
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val |= FIELD_PREP(LRCLK_DIV_FIELD, adata->lrclk_div);
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val |= FIELD_PREP(BCLK_DIV_FIELD, adata->bclk_div);
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}
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writel(val, adata->acp_base + i2s_clk_reg);
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}
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