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drm/i915/gt: Flush before changing register state
Flush; invalidate; change registers; invalidate; flush.
Will this finally work on every device? Or will Baytrail complain again?
On the positive side, we immediately see the benefit of having hsw-gt1 in
CI.
Fixes: ace44e13e5
("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals")
Testcase: igt/gem_render_tiled_blits # hsw-gt1
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210125220247.31701-1-chris@chris-wilson.co.uk
(cherry picked from commit d30bbd62b1bfd9e0a33c3583c5a9e5d66f60cbd7)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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@ -393,6 +393,7 @@ static void emit_batch(struct i915_vma * const vma,
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desc_count);
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/* Reset inherited context registers */
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gen7_emit_pipeline_flush(&cmds);
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gen7_emit_pipeline_invalidate(&cmds);
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batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));
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batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));
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