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MIPS: mscc: Add ocelot dtsi
Add a device tree include file for the Microsemi Ocelot SoC. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Allan Nielsen <Allan.Nielsen@microsemi.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/18855/ Signed-off-by: James Hogan <jhogan@kernel.org>
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3 changed files with 119 additions and 0 deletions
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@ -4,6 +4,7 @@ subdir-y += cavium-octeon
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subdir-y += img
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subdir-y += img
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subdir-y += ingenic
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subdir-y += ingenic
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subdir-y += lantiq
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subdir-y += lantiq
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subdir-y += mscc
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subdir-y += mti
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subdir-y += mti
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subdir-y += netlogic
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subdir-y += netlogic
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subdir-y += ni
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subdir-y += ni
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1
arch/mips/boot/dts/mscc/Makefile
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1
arch/mips/boot/dts/mscc/Makefile
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@ -0,0 +1 @@
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obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
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117
arch/mips/boot/dts/mscc/ocelot.dtsi
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117
arch/mips/boot/dts/mscc/ocelot.dtsi
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2017 Microsemi Corporation */
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mscc,ocelot";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "mips,mips24KEc";
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device_type = "cpu";
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clocks = <&cpu_clk>;
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reg = <0>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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cpu_clk: cpu-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <500000000>;
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};
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ahb_clk: ahb-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&cpu_clk>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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ahb@70000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x70000000 0x2000000>;
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interrupt-parent = <&intc>;
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cpu_ctrl: syscon@0 {
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compatible = "mscc,ocelot-cpu-syscon", "syscon";
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reg = <0x0 0x2c>;
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};
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intc: interrupt-controller@70 {
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compatible = "mscc,ocelot-icpu-intr";
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reg = <0x70 0x70>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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uart0: serial@100000 {
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pinctrl-0 = <&uart_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100000 0x20>;
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interrupts = <6>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart2: serial@100800 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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compatible = "ns16550a";
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reg = <0x100800 0x20>;
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interrupts = <7>;
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clocks = <&ahb_clk>;
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reg-io-width = <4>;
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reg-shift = <2>;
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status = "disabled";
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};
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reset@1070008 {
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compatible = "mscc,ocelot-chip-reset";
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reg = <0x1070008 0x4>;
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};
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gpio: pinctrl@1070034 {
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compatible = "mscc,ocelot-pinctrl";
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reg = <0x1070034 0x68>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 22>;
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uart_pins: uart-pins {
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pins = "GPIO_6", "GPIO_7";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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pins = "GPIO_12", "GPIO_13";
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function = "uart2";
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};
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};
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};
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};
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