clk: qcom: gcc-qdu1000: Fix clkref clocks handling
[ Upstream commit2524dae5cd
] Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's status bit is not inverted in the latest hardware version of QDU1000 and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well. Fixes:1c9efb0bc0
("clk: qcom: Add QDU1000 and QRU1000 GCC support") Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230803105741.2292309-4-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -1447,14 +1447,13 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
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static struct clk_branch gcc_pcie_0_clkref_en = {
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static struct clk_branch gcc_pcie_0_clkref_en = {
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.halt_reg = 0x9c004,
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.halt_reg = 0x9c004,
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.halt_bit = 31,
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.halt_check = BRANCH_HALT,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.clkr = {
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.enable_reg = 0x9c004,
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.enable_reg = 0x9c004,
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.enable_mask = BIT(0),
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.hw.init = &(const struct clk_init_data) {
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.name = "gcc_pcie_0_clkref_en",
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.name = "gcc_pcie_0_clkref_en",
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.ops = &clk_branch_ops,
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.ops = &clk_branch2_ops,
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},
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},
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},
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},
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};
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};
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@ -2274,14 +2273,13 @@ static struct clk_branch gcc_tsc_etu_clk = {
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static struct clk_branch gcc_usb2_clkref_en = {
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static struct clk_branch gcc_usb2_clkref_en = {
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.halt_reg = 0x9c008,
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.halt_reg = 0x9c008,
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.halt_bit = 31,
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.halt_check = BRANCH_HALT,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.clkr = {
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.enable_reg = 0x9c008,
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.enable_reg = 0x9c008,
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.enable_mask = BIT(0),
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.hw.init = &(const struct clk_init_data) {
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.name = "gcc_usb2_clkref_en",
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.name = "gcc_usb2_clkref_en",
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.ops = &clk_branch_ops,
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.ops = &clk_branch2_ops,
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},
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},
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},
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},
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};
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};
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