This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve as
the first input of the clock outputs, which according to AW's A20 user
manual, is the 24MHz oscillator divided by 750.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Device tree naming conventions state that node names should match
the nodes function. Change external low speed oscillator node name
to match.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch adds the clock output pin options on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allwinner sunXi SoCs DT changes for clocks
This contains the DT parts of the "[PATCH v3 00/13] clk: sunxi: add PLL5
and PLL6 support" series. It adds DT nodes for PLL4/5/6 and mod0 clocks
on most sunxi platforms.
mbus is the memory bus clock, and it is present on both sun5i and sun7i
machines. Its register layout is compatible with the mod0 one.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds all the mod0 clocks available on A20 to its device
tree. This list was created by looking at AW's code release.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
device trees.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
device trees. PLL4 is compatible with PLL1.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A20 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A20 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Cc: stable@vger.kernel.org #3.12+
Signed-off-by: Olof Johansson <olof@lixom.net>
The Allwinner A20 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.
Now that we have a driver to support it, we can enable them in the
device tree.
[dlezcano] : Fixed conflict with 428abbb8 "Enable the I2C controllers"
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
U-Boot uses the ethernet0 alias to locate the right node to fill in
the MAC address of the first ethernet interface. This patch adds the
alias on all the sunxi SoCs with EMAC. In this way, people using
ethernet in U-Boot (eg, for tftp) can keep a consistent address on both
U-Boot and Linux with no additional effort.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the RTC node to DTS for Allwinner A10 and Allwinner A20.
Signed-off-by: Carlo Caione <carlo.caione@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20 boards we currently have share the same pins for the i2c
controllers they share. Add them to the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A20 shares the same I2C controller than the one that could
be found on earlier SoCs from Allwinner. There is only a few more of
these controllers. Add all of them in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch shall add support for the sunxi-sid driver to the device
tree for A10, A10s, A13 and A20.
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A20 has several muxing options for the EMAC. Yet, the currently
supported boards only use one set of them. Add that pin set to the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The Allwinner A20 SoC also have the EMAC found on the A10 and A10s.
Enable the support for it in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Now that the clock driver knows about the available clocks found on the
A20, we can build up the clock tree from the device tree.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The UARTs on the A20 can be muxed to several pins. Add a few options to
the DTSI so that we can start using them in the boards' DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The PIO controller is responsible for the GPIO/muxing/external
interrupts handling. Now that we have support for the A20 pin set in the
pinctrl driver, we can start using it in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The Allwinner A20 SoC is based on 2 Cortex A7, an ARM Mali GPU, and is
built to be pin-compatible with the older Allwinner A10.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
