Commit graph

948960 commits

Author SHA1 Message Date
周琰杰 (Zhou Yanjie)
2372b50611 dt-bindings: MIPS: Add X2000E based CU2000-Neo.
Add bindings for Ingenic X2000E based board, prepare for later dts.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-27 10:56:32 +02:00
Thomas Bogendoerfer
063a9966ee Revert "MIPS: OCTEON: use devm_platform_ioremap_resource"
This reverts commit 0ee69c589e.

Resource is still needed later in the code, so using
devm_platform_ioremap_resource is no win at all.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-23 09:26:44 +02:00
Youling Tang
2626239614 MIPS: kexec: Add crashkernel=YM handling
When the kernel crashkernel parameter is specified with just a size,
we are supposed to allocate a region from RAM to store the crashkernel.
However, MIPS merely reserves physical address zero with no checking
that there is even RAM there.

Fix this by lifting similar code from x86, importing it to MIPS with the
MIPS specific parameters added. In the absence of any platform specific
information, we allocate the crashkernel region from the first 512MB of
physical memory (limited to CKSEG0 or KSEG0 address range).

When X is not specified, crash_base defaults to 0 (crashkernel=YM@XM).

E.g. without this patch:

The environment as follows:
[    0.000000] MIPS: machine is loongson,loongson64c-4core-ls7a
...
[    0.000000] Kernel command line: root=/dev/sda2 crashkernel=96M ...

The warning as follows:
[    0.000000] Invalid memory region reserved for crash kernel

And the iomem as follows:
00200000-0effffff : System RAM
  00200000-00b47f87 : Kernel code
  00b47f88-00dfffff : Kernel data
  00e60000-01f73c7f : Kernel bss
1a000000-1bffffff : pci@1a000000
...

With this patch:

After increasing crash_base <= 0 handling.

And the iomem as follows:
00200000-0effffff : System RAM
  00200000-00b47f87 : Kernel code
  00b47f88-00dfffff : Kernel data
  00e60000-01f73c7f : Kernel bss
  04000000-09ffffff : Crash kernel
1a000000-1bffffff : pci@1a000000
...

Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:40:07 +02:00
Tiezhu Yang
5fa1f7680f MIPS: Loongson64: Add UART node for LS7A PCH
When I update the latest kernel on the Loongson platform used with
LS7A bridge chip, the serial console has no output, this is because
the machine uses LS7A UART0 instead of CPU UART0, add UART node for
LS7A PCH to enhance the compatibility.

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:19:07 +02:00
周琰杰 (Zhou Yanjie)
c1f6b45e63 MIPS: Ingenic: Add CPU nodes for Ingenic SoCs.
Add 'cpus' node to the jz4725b.dtsi, jz4740.dtsi, jz4770.dtsi,
jz4780.dtsi, x1000.dtsi, and x1830.dtsi files.

Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:17:38 +02:00
Thomas Bogendoerfer
307c992639 MIPS: malta: remove mach-malta/malta-dtshim.h header file
To clean up mach-* directories move external declaration of malta_dt_shim()
to mips-boards/malta.h and remove malta-dtshim.h.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:16:47 +02:00
Thomas Bogendoerfer
0c0938ea1d MIPS: malta: remove unused header file
Remove unused heasder file asm/mach-malta/malta-pm.h.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:16:38 +02:00
Thomas Bogendoerfer
b350041e6f MIPS: alchemy: remove unused ALCHEMY_GPIOINT_AU1000
Remove unused config option ALCHEMY_GPIOINT_AU1000.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:16:28 +02:00
Thomas Bogendoerfer
b123c46cf5 MIPS: alchemy: remove unused ALCHEMY_GPIOINT_AU1300
Remove unused config option ALCHEMY_GPIOINT_AU1300 and related code.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:16:11 +02:00
Thomas Bogendoerfer
7895d662ba MIPS: SGI-IP30: Move irq bits to better header files
Move HEART specific parts of mach-ip30/irq.h to asm/sgi/heart.h and IP30
specific parts to sgi-ip30/ip30-common.h.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:15:49 +02:00
Huacai Chen
bc1c969f11 MIPS: Loongson-3: Calculate ra properly when unwinding the stack
Loongson-3 has 16-bytes load/store instructions: gslq and gssq. This
patch calculate ra properly when unwinding the stack, if ra is saved
by gssq and restored by gslq.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:15:22 +02:00
Huacai Chen
195615ecc8 MIPS: Loongson-3: Enable COP2 usage in kernel
Loongson-3's COP2 is Multi-Media coprocessor, it is disabled in kernel
mode by default. However, gslq/gssq (16-bytes load/store instructions)
overrides the instruction format of lwc2/swc2. If we wan't to use gslq/
gssq for optimization in kernel, we should enable COP2 usage in kernel.

Please pay attention that in this patch we only enable COP2 in kernel,
which means it will lose ST0_CU2 when a process go to user space (try
to use COP2 in user space will trigger an exception and then grab COP2,
which is similar to FPU). And as a result, we need to modify the context
switching code because the new scheduled process doesn't contain ST0_CU2
in its THERAD_STATUS probably.

For zboot, we disable gslq/gssq be generated by toolchain.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:15:03 +02:00
Huacai Chen
4e43e5df58 MIPS: context switch: Use save/restore instead of set/clear for Status.CU2
Some processors (such as Loongson-3) need to enable CU2 in kernel mode,
current set/clear method will lose Status.CU2 during context switching,
so use save/restore method instead.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:14:47 +02:00
Pujin Shi
6fa573a3e3 MIPS: kernel: include probes-common.h header in branch.c
arch/mips/kernel/branch.c:876:5: error: no previous prototype for '__insn_is_compact_branch' [-Werror=missing-prototypes]

Signed-off-by: Pujin Shi <shipujin.t@gmail.com>
Signed-off-by: Pujin Shi <shipj@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:14:24 +02:00
Jason Yan
d976ae6ba0 MIPS: Make setup_elfcorehdr and setup_elfcorehdr_size static
This addresses the following sparse warning:

arch/mips/kernel/setup.c:446:33: warning: symbol 'setup_elfcorehdr_size'
was not declared. Should it be static?

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-21 22:08:18 +02:00
Paul Cercueil
d41afc398f MAINTAINERS: Update paths to Ingenic platform code
Support for Ingenic chips has been moved to the generic MIPS platform.
Update the paths accordingly.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:35:45 +02:00
Paul Cercueil
8446fd61b5 MIPS: configs: Regenerate configs of Ingenic boards
For each board the MACH_INGENIC_SOC option was selected instead of
MACH_INGENIC. Nothing else was changed in the menuconfig.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:35:27 +02:00
Paul Cercueil
a103e9b951 MIPS: jz4740: Rename jz4740 folders to ingenic
Now that all the jz4740 platform code has been removed, and we're left
with only a Kconfig and the cpu-feature-overrides.h file, finalize the
cleanup process by renaming the jz4740 and include/mach-jz4740 folders
to ingenic and include/mach-ingenic.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:35:05 +02:00
Paul Cercueil
b4a30e9c74 MIPS: jz4740: Drop all obsolete files
Support for Ingenic SoCs is now provided by the arch/mips/generic/ code,
so all files in the arch/mips/jz4740/ folder can dropped, except for the
Kconfig, and the cpu-feature-overrides.h header file.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:34:32 +02:00
Paul Cercueil
f0f4a75307 MIPS: generic: Add support for Ingenic SoCs
Add support for Ingenic SoCs in arch/mips/generic/.

The Kconfig changes are here to ensure that it is possible to compile
either a generic kernel that supports Ingenic SoCs, or a Ingenic-only
kernel, both using the same code base, to avoid duplicated code.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:33:59 +02:00
Paul Cercueil
02bd530f88 MIPS: generic: Increase NR_IRQS to 256
128 IRQs is not enough to support Ingenic SoCs.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:33:35 +02:00
Paul Cercueil
c3e2ee6574 MIPS: generic: Add support for zboot
There is no reason we can't create compressed kernels here, so select
the option SYS_SUPPORTS_ZBOOT.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:33:06 +02:00
Paul Cercueil
323690d23b MIPS: generic: Support booting with built-in or appended DTB
The plat_get_fdt() checked that the kernel was booted using UHI before
reading the 'fw_passed_dtb' variable. However, this variable is also set
when the DT has been appended, or when it has been built into the kernel.

Support these usecases by removing the UHI check.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:32:19 +02:00
Paul Cercueil
13a0ea28e8 MIPS: generic: Init command line with fw_init_cmdline()
The function bootcmdline_init() in arch/mips/kernel/setup.c will
populate the boot_command_line string using the parameters hardcoded in
the kernel, and those provided in the devicetree file. Then, it would
append the content of the arcs_cmdline variable, which is filled by the
board's plat_mem_setup() function.

The plat_mem_setup() function for the generic MIPS board would just copy
the current boot_command_line to arcs_cmdline, which is nonsense for two
reasons:
- the result will be appended to the boot_command_line anyway, so all it
  does is duplicate every single parameter on the command line;
- the code did not perform at all what it's supposed to, which is to
  retrieve the parameters passed by the bootloader.

Fix this by calling fw_init_cmdline() in plat_mem_setup(), which will
properly initialize arcs_cmdline to the parameters passed by the
bootloader.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:31:10 +02:00
Paul Cercueil
8405419942 MIPS: generic: Allow boards to set system type
Check for the system_type variable in the get_system_type() function. If
non-NULL, return it as the system type.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:28:56 +02:00
Paul Cercueil
c434b9f80b MIPS: Kconfig: add MIPS_GENERIC_KERNEL symbol
The MIPS_GENERIC symbol now won't select any other configuration option.
The MIPS_GENERIC_KERNEL will select all the options that the previous
MIPS_GENERIC option did select, and will select MIPS_GENERIC as well.

The whole point of this, is that it now becomes possible to compile a
kernel for a SoC supported by the arch/mips/generic/ code, without
making that kernel generic itself.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:28:31 +02:00
Paul Cercueil
5f5ed0ebcf MIPS: cpu-probe: ingenic: Fix broken BUG_ON
The previous code was doing:
BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);

This only worked as the "cpu_has_counter" macro was overridden in
<cpu-feature-overrides.h>. The default "cpu_has_counter" macro is
non-constant, which triggered the BUG_ON() independently of the value
returned by the macro.

What we want to check here, is that *if* the macro was overridden to a
compile-time constant, then must be defined to zero, otherwise it's a
bug.

So the correct check is:
BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:27:32 +02:00
Paul Cercueil
5ef415107d MIPS: cpu-probe: Mark XBurst CPU as having vtagged caches
XBurst CPUs present in Ingenic SoCs have virtually tagged caches,
according to the <cpu-features-override.h> header.

Add that information to cpu_probe_ingenic().

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:27:00 +02:00
Paul Cercueil
95b1f6db67 MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA
Previously, in cpu_probe_ingenic(), c->writecombine was set to
_CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when
CONFIG_MACH_INGENIC was set. This made it impossible to support multiple
CPUs.

Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA
directly and removing the dependency on CONFIG_MACH_INGENIC.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:26:36 +02:00
Paul Cercueil
7487abbe85 MIPS: configs: lb60: Fix defconfig not selecting correct board
Since INGENIC_GENERIC_BOARD was introduced, the JZ4740_QI_LB60 option
is no longer the default, so the symbol has to be selected by the
defconfig, otherwise the kernel built will be for a generic Ingenic
board and won't have the Device Tree blob built-in.

Cc: stable@vger.kernel.org # v5.7
Fixes: 62249209a7 ("MIPS: ingenic: Default to a generic board")
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 16:26:12 +02:00
Huacai Chen
055444c266 MIPS: Loongson64: Increase NR_IRQS to 320
Modernized Loongson64 uses a hierarchical organization for interrupt
controllers (INTCs), all INTC nodes (not only leaf nodes) need some IRQ
numbers. This means 280 (i.e., NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + 256)
is not enough to represent all interrupts, so let's increase NR_IRQS to
320 (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256).

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 15:36:02 +02:00
Youling Tang
338a93a497 MIPS: netlogic: Remove unused code
Remove some unused code.

Signed-off-by: Youling Tang <tangyouling@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 15:31:20 +02:00
Qinglang Miao
0ee69c589e MIPS: OCTEON: use devm_platform_ioremap_resource
Note that error handling on the result of a call to platform_get_resource()
is unneeded when the value is passed to devm_ioremap_resource(), so remove
it. Then use the helper function that wraps the calls to
platform_get_resource() and devm_ioremap_resource() together.

Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 15:30:41 +02:00
Zhang Qilong
b0a1c2903b MIPS: pci: use devm_platform_ioremap_resource_byname
Use the devm_platform_ioremap_resource_byname() helper instead of
calling platform_get_resource_byname() and devm_ioremap_resource()
separately.

Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 15:29:35 +02:00
Wei Li
38a6445cab MIPS: Correct the header guard of r4k-timer.h
Rename the header guard of r4k-timer.h from __ASM_R4K_TYPES_H to
__ASM_R4K_TIMER_H what corresponding with the file name.

Signed-off-by: Wei Li <liwei391@huawei.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-18 15:29:00 +02:00
Thomas Bogendoerfer
601637e42d MIPS: Remove mach-*/war.h
After conversion of all WAR defines we can now remove all mach-*/war.h
files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:25:27 +02:00
Thomas Bogendoerfer
8e7291d603 MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR
CAVIUM_OCTEON_DCACHE_PREFETCH_WAR is a check for Octeon model CN6XXXX.
By using the version check we can remove the define.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:25:16 +02:00
Thomas Bogendoerfer
ab5743079b MIPS: Get rid of BCM1250_M3_WAR
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS.
So using this option directly lets and remove define.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:25:03 +02:00
Thomas Bogendoerfer
43df4eb2fc MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS
SB1250 uart bug is related to PASS 2 workarounds. Use config
CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:51 +02:00
Thomas Bogendoerfer
a7fbed988f MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option
Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:40 +02:00
Thomas Bogendoerfer
256ec489f1 MIPS: Convert R10000_LLSC_WAR info a config option
Use a new config option to enabel R1000_LLSC workaound and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:27 +02:00
Thomas Bogendoerfer
886ee1363a MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option
Use a new config option to enable I-cache refill workaround and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:19 +02:00
Thomas Bogendoerfer
24a1c023f3 MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option
Use a new config option to enable TX49XX I-cache index invalidate
workaround and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:09 +02:00
Thomas Bogendoerfer
142439b052 MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented,
so removing defines for it won't change anything.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:24:01 +02:00
Thomas Bogendoerfer
44def3426e MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:23:48 +02:00
Thomas Bogendoerfer
5e5b652712 MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:23:38 +02:00
Thomas Bogendoerfer
802b83627f MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
Use a new config option to enable R4600 V1 index I-cacheop workaround
and remove define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:23:29 +02:00
Paul Cercueil
8c2ede45ed MIPS: dts/ingenic: Cleanup qi_lb60.dts
Cleanup a bit the Device Tree file:

1. Respect the number of cells in GPIO descriptors and keyboard matrix;
2. Use 'ecc-engine' instead of deprecated 'ingenic,bch-controller'
   property;
3. The NAND's rb-gpios is actually active high;
3. The FRE/FWE pins must be configured in the proper mode for the NAND
   to work if it was not already done by the bootloader.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:18:24 +02:00
Jinyang He
263cdc37c1 MIPS: Loongson64: Remove unused loongson_reboot.
Commit 1bdb7b7670 ("MIPS: Loongson64: Cleanup unused code")
left the loongson_reboot unused, delete it.

Signed-off-by: Jinyang He <hejinyang@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-07 22:17:12 +02:00
Jinyang He
af07fabdd2 MIPS: p5600: Discard UCA config selection
Commit 2a5984360b ("MIPS: Drop CPU_SUPPORTS_UNCACHED_ACCELERATED")
removed UCA config, but left the selection unused, delete it.

Signed-off-by: Jinyang He <hejinyang@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-09-03 10:14:07 +02:00