[ Upstream commit 4712eb7ff8 ]
There are 10 more GDSCs that we've not been caring about, and by extension
(and perhaps even more importantly), not putting to sleep. Add them.
Fixes: d65d005f9a ("clk: qcom: add sc8280xp GCC driver")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230620-topic-sc8280_gccgdsc-v2-3-562c1428c10d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 2fd02de270 ]
All of the 8280's GCC GDSCs can and should use the retain registers so
as not to lose their state when entering lower power modes.
Fixes: d65d005f9a ("clk: qcom: add sc8280xp GCC driver")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230620-topic-sc8280_gccgdsc-v2-1-562c1428c10d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
The three UFS reference clocks, gcc_ufs_ref_clkref_clk for external
UFS devices, gcc_ufs_card_clkref_clk and gcc_ufs_1_card_clkref_clk for
two PHYs are all sourced from CXO.
Added parent_data for all three reference clocks described above to
reflect that all three clocks are sourced from CXO to have valid
frequency for the ref clock needed by UFS controller driver.
Fixes: d65d005f9a ("clk: qcom: add sc8280xp GCC driver")
Link: https://lore.kernel.org/lkml/Y2Tber39cHuOSR%2FW@hovoldconsulting.com/
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20221115152956.21677-1-quic_shazhuss@quicinc.com
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Since commit d399723950 ("clk: qcom: gdsc: Fix the handling of
PWRSTS_RET support) retention mode can be used on sc8280xp to maintain
state during suspend instead of leaving the domain always on.
This is needed to eventually allow the parent CX domain to be powered
down during suspend.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220929161124.18138-1-johan+linaro@kernel.org
The Qualcomm DWC3 driver suspend implementation appears to be incomplete
for SC8280XP so keep the USB power domains always-on for now so that the
controller survives a suspend cycle.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220805121250.10347-3-johan+linaro@kernel.org
The Qualcomm PCIe driver does not yet implement suspend so to keep the
PCIe power domains always-on for now to avoid crashing during resume.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220805121250.10347-2-johan+linaro@kernel.org
Use the new phy-mux clock implementation for the PCIe pipe clock muxes
so that the pipe clock source is set to the QMP PHY PLL when the
downstream pipe clock is enabled and restored to the always-on XO when
it is again disabled.
This is needed to prevent the corresponding GDSC from hanging when
enabling or disabling the PCIe power domain, something which requires a
ticking source.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220628085707.16214-1-johan+linaro@kernel.org
The PCIe GDSCs can be shared with other masters and should use the APCS
collapse-vote register when updating the power state.
This is specifically also needed to be able to disable power domains
that have been enabled by boot firmware using the vote register.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220520100948.19622-4-johan+linaro@kernel.org
Add support for the Global Clock Controller found in the Qualcomm
SC8280XP platform.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220505025457.1693716-3-bjorn.andersson@linaro.org
