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Author SHA1 Message Date
Linus Torvalds
b611996ef2 linux-watchdog 6.2-rc1 tag 
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Merge tag 'linux-watchdog-6.2-rc1' of git://www.linux-watchdog.org/linux-watchdog

Pull watchdog updates from Wim Van Sebroeck:

 - Add Advantech EC watchdog driver

 - Add support for MT6795 Helio X10 watchdog and toprgu

 - Add support for MT8188 watchdog device

 - Remove #ifdef guards for PM related functions

 - Other fixes and improvements

* tag 'linux-watchdog-6.2-rc1' of git://www.linux-watchdog.org/linux-watchdog:
  watchdog: aspeed: Enable pre-timeout interrupt
  watchdog: iTCO_wdt: Set NO_REBOOT if the watchdog is not already running
  watchdog: rn5t618: add support for read out bootstatus
  watchdog: kempld: Remove #ifdef guards for PM related functions
  watchdog: omap: Remove #ifdef guards for PM related functions
  watchdog: twl4030: Remove #ifdef guards for PM related functions
  watchdog: at91rm9200: Remove #ifdef guards for PM related functions
  watchdog: Add Advantech EC watchdog driver
  dt-bindings: watchdog: mediatek,mtk-wdt: Add compatible for MT8173
  dt-bindings: watchdog: mediatek,mtk-wdt: Add compatible for MT6795
  dt-bindings: watchdog: mediatek: Convert mtk-wdt to json-schema
  watchdog: mediatek: mt8188: add wdt support
  dt-bindings: reset: mt8188: add toprgu reset-controller header file
  dt-bindings: watchdog: Add compatible for MediaTek MT8188
  watchdog: mtk_wdt: Add support for MT6795 Helio X10 watchdog and toprgu
 2022-12-17 08:34:01 -06:00
Linus Torvalds
0015edd6f6 A pile of clk driver updates with a small tracepoint patch to the clk core this 
time around. The core framework is effectively unchanged, with the majority of
 the diff going to the Qualcomm clk driver directory because they added two 3k
 line files that are almost all clk data (Abel Vesa from Linaro tried to shrink
 the number of lines down, but it doesn't seem to be possible without
 sacrificing readability). The second big driver this time around is the
 Rockchip rk3588 clk and reset unit, at _only_ 2.5k lines.
 
 Ignoring the big clk drivers from the familiar SoC vendors, there's just a
 bunch of little clk driver updates and fixes throughout here. It's the usual
 set of clk data fixups to describe proper parents, or add frequencies to
 frequency tables, or plug memory leaks when function calls fail. Also, some
 drivers are converted to use modern clk_hw APIs, which is always nice to see.
 And data is deduplicated, leading to a smaller kernel Image. Overall this batch
 has a larger collection of cleanups than it typically does. Maybe that means
 there are less new SoCs right now that need supporting, and the focus has
 shifted to quality and reliability. I can dream.
 
 New Drivers:
  - Frequency hopping controller hardware on MediaTek MT8186
  - Global clock controller for Qualcomm SM8550
  - Display clock controller for Qualcomm SC8280XP
  - RPMh clock controller for Qualcomm QDU1000 and QRU1000 SoCs
  - CPU PLL on MStar/SigmaStar SoCs
  - Support for the clock and reset unit of the Rockchip rk3588
 
 Updates:
  - Tracepoints for clk_rate_request structures
  - Debugfs support for fractional divider clk
  - Make MxL's CGU driver secure compatible
  - Ingenic JZ4755 SoC clk support
  - Support audio clks on X1000 SoCs
  - Remove flags from univ/main/syspll child fixed factor clocks across
    MediaTek platforms
  - Fix clock dependency for ADC on MediaTek MT7986
  - Fix parent for FlexSPI clock for i.MX93
  - Add USB suspend clock on i.MX8MP
  - Unmap anatop base on error for i.MX93 driver
  - Change enet clock parent to wakeup_axi_root for i.MX93
  - Drop LPIT1, LPIT2, TPM1 and TPM3 clocks for i.MX93
  - Mark HSIO bus clock and SYS_CNT clock as critical on i.MX93
  - Add 320MHz and 640MHz entries to PLL146x
  - Add audio shared gate and SAI clocks for i.MX8MP
  - Fix a possible memory leak in the error path of rockchip PLL creation
  - Fix header guard for V3S clocks
  - Add IR module clock for f1c100s
  - Correct the parent clocks for the (High Speed) Serial Communication
    Interfaces with FIFO ((H)SCIF) modules and the mixed-up Ethernet
    Switch clocks on Renesas R-Car S4-8
  - Add timer (TMU, CMT) and Cortex-A76 CPU core (Z0) clocks on Renesas
    R-Car V4H
  - Two PLL driver fixups for the Amlogic clk driver
  - Round SD clock rate to improve parent clock selection
  - Add Ethernet Switch and internal SASYNCPER clocks on Renesas R-Car
    S4-8
  - Add DMA (SYS-DMAC), SPI (MSIOF), external interrupt (INTC-EX) serial
    (SCIF), PWM (PWM and TPU), SDHI, and HyperFLASH/QSPI (RPC-IF) clocks
    on Renesas R-Car V4H
  - Add Multi-Function Timer Pulse Unit (MTU3a) clock and reset on
    Renesas RZ/G2L
  - Fix endless loop on Renesas RZ/N1
  - Correct the parent clocks for the High Speed Serial Communication
    Interfaces with FIFO (HSCIF) modules on the Renesas R-Car V4H SoC
    Note: HSCIF0 is used for the serial console on the White-Hawk
    development board
  - Various clk DT binding improvements and conversions to YAML
  - Qualcomm SM8150/SM8250 display clock controller cleaned up
  - Some missing clocks for Qualcomm SM8350 added
  - Qualcomm MSM8974 Global and Multimedia clock controllers transitioned
    to parent_data and parent_hws
  - Use parent_data and add network resets for Qualcomm IPQ8074
  - Qualcomm Krait clock controller modernized
  - Fix pm_runtime usage in Qualcomm SC7180 and SC7280 LPASS clock
    controllers
  - Enable retention mode on Qualcomm SM8250 USB GDSCs
  - Cleanup Qualcomm RPM and RPMh clock drivers to avoid duplicating
    clocks which definition could be shared between platforms
  - Various NULL pointer checks added for allocations
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk driver updates from Stephen Boyd:
 "A pile of clk driver updates with a small tracepoint patch to the clk
  core this time around.

  The core framework is effectively unchanged, with the majority of the
  diff going to the Qualcomm clk driver directory because they added two
  3k line files that are almost all clk data (Abel Vesa from Linaro
  tried to shrink the number of lines down, but it doesn't seem to be
  possible without sacrificing readability).

  The second big driver this time around is the Rockchip rk3588 clk and
  reset unit, at _only_ 2.5k lines.

  Ignoring the big clk drivers from the familiar SoC vendors, there's
  just a bunch of little clk driver updates and fixes throughout here.

  It's the usual set of clk data fixups to describe proper parents, or
  add frequencies to frequency tables, or plug memory leaks when
  function calls fail. Also, some drivers are converted to use modern
  clk_hw APIs, which is always nice to see. And data is deduplicated,
  leading to a smaller kernel Image.

  Overall this batch has a larger collection of cleanups than it
  typically does. Maybe that means there are less new SoCs right now
  that need supporting, and the focus has shifted to quality and
  reliability. I can dream.

  New Drivers:
   - Frequency hopping controller hardware on MediaTek MT8186
   - Global clock controller for Qualcomm SM8550
   - Display clock controller for Qualcomm SC8280XP
   - RPMh clock controller for Qualcomm QDU1000 and QRU1000 SoCs
   - CPU PLL on MStar/SigmaStar SoCs
   - Support for the clock and reset unit of the Rockchip rk3588

  Updates:
   - Tracepoints for clk_rate_request structures
   - Debugfs support for fractional divider clk
   - Make MxL's CGU driver secure compatible
   - Ingenic JZ4755 SoC clk support
   - Support audio clks on X1000 SoCs
   - Remove flags from univ/main/syspll child fixed factor clocks across
     MediaTek platforms
   - Fix clock dependency for ADC on MediaTek MT7986
   - Fix parent for FlexSPI clock for i.MX93
   - Add USB suspend clock on i.MX8MP
   - Unmap anatop base on error for i.MX93 driver
   - Change enet clock parent to wakeup_axi_root for i.MX93
   - Drop LPIT1, LPIT2, TPM1 and TPM3 clocks for i.MX93
   - Mark HSIO bus clock and SYS_CNT clock as critical on i.MX93
   - Add 320MHz and 640MHz entries to PLL146x
   - Add audio shared gate and SAI clocks for i.MX8MP
   - Fix a possible memory leak in the error path of rockchip PLL
     creation
   - Fix header guard for V3S clocks
   - Add IR module clock for f1c100s
   - Correct the parent clocks for the (High Speed) Serial Communication
     Interfaces with FIFO ((H)SCIF) modules and the mixed-up Ethernet
     Switch clocks on Renesas R-Car S4-8
   - Add timer (TMU, CMT) and Cortex-A76 CPU core (Z0) clocks on Renesas
     R-Car V4H
   - Two PLL driver fixups for the Amlogic clk driver
   - Round SD clock rate to improve parent clock selection
   - Add Ethernet Switch and internal SASYNCPER clocks on Renesas R-Car
     S4-8
   - Add DMA (SYS-DMAC), SPI (MSIOF), external interrupt (INTC-EX)
     serial (SCIF), PWM (PWM and TPU), SDHI, and HyperFLASH/QSPI
     (RPC-IF) clocks on Renesas R-Car V4H
   - Add Multi-Function Timer Pulse Unit (MTU3a) clock and reset on
     Renesas RZ/G2L
   - Fix endless loop on Renesas RZ/N1
   - Correct the parent clocks for the High Speed Serial Communication
     Interfaces with FIFO (HSCIF) modules on the Renesas R-Car V4H SoC
     Note: HSCIF0 is used for the serial console on the White-Hawk
     development board
   - Various clk DT binding improvements and conversions to YAML
   - Qualcomm SM8150/SM8250 display clock controller cleaned up
   - Some missing clocks for Qualcomm SM8350 added
   - Qualcomm MSM8974 Global and Multimedia clock controllers
     transitioned to parent_data and parent_hws
   - Use parent_data and add network resets for Qualcomm IPQ8074
   - Qualcomm Krait clock controller modernized
   - Fix pm_runtime usage in Qualcomm SC7180 and SC7280 LPASS clock
     controllers
   - Enable retention mode on Qualcomm SM8250 USB GDSCs
   - Cleanup Qualcomm RPM and RPMh clock drivers to avoid duplicating
     clocks which definition could be shared between platforms
   - Various NULL pointer checks added for allocations"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (188 commits)
  clk: nomadik: correct struct name kernel-doc warning
  clk: lmk04832: fix kernel-doc warnings
  clk: lmk04832: drop superfluous #include
  clk: lmk04832: drop unnecessary semicolons
  clk: lmk04832: declare variables as const when possible
  clk: socfpga: Fix memory leak in socfpga_gate_init()
  clk: microchip: enable the MPFS clk driver by default if SOC_MICROCHIP_POLARFIRE
  clk: st: Fix memory leak in st_of_quadfs_setup()
  clk: samsung: Fix memory leak in _samsung_clk_register_pll()
  clk: Add trace events for rate requests
  clk: Store clk_core for clk_rate_request
  clk: qcom: rpmh: add support for SM6350 rpmh IPA clock
  clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: mmcc-msm8974: move clock parent tables down
  clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: gcc-msm8974: move clock parent tables down
  clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974
  dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file
  ...
 2022-12-13 13:46:07 -08:00
Jon Hunter
41155b6f6d dt-bindings: tegra: Update headers for Tegra234 
Update the device-tree clock, memory, power and reset headers for
Tegra234 by adding the definitions for all the various devices.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2022-11-21 13:27:17 +01:00
Runyang Chen
fea58041af dt-bindings: reset: mt8188: add toprgu reset-controller header file 
Add toprgu reset-controller header file for MT8188

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20221026063327.20037-3-Runyang.Chen@mediatek.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
 2022-11-19 15:30:35 +01:00
Sebastian Reichel
0a8eb7dae6 dt-bindings: reset: add rk3588 reset definitions 
Add reset ID defines for rk3588.

Compared to the downstream bindings and previous rockchip
generations this uses continous gapless reset IDs starting
at 0 instead of register offsets as IDs. Thus all numbers
are different between upstream and downstream, but I kept
the names exactly the same.

Co-Developed-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-3-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2022-11-14 15:28:47 +01:00
Mikko Perttunen
0e2b014eeb dt-bindings: Add headers for NVDEC on Tegra234 
Add clock, memory controller, powergate and reset dt-binding headers
necessary for NVDEC.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2022-10-24 14:53:35 +02:00
Stephen Boyd
f9efefdba9 Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versaclock' into clk-next 
- Convert Baikal-T1 CCU driver to platform driver
 - Split reset support out of primary Baikal-T1 CCU driver
 - Add some missing clks required for RPiVid Video Decoder on RaspberryPi
 - Mark PLLC critical on bcm2835
 - Support for Renesas VersaClock7 clock generator family

* clk-baikal:
  clk: baikal-t1: Convert to platform device driver
  clk: baikal-t1: Add DDR/PCIe directly controlled resets support
  dt-bindings: clk: baikal-t1: Add DDR/PCIe reset IDs
  clk: baikal-t1: Move reset-controls code into a dedicated module
  clk: baikal-t1: Add SATA internal ref clock buffer
  clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent
  clk: baikal-t1: Fix invalid xGMAC PTP clock divider
  clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD

* clk-broadcom:
  clk: bcm: rpi: Add support for VEC clock
  clk: bcm: rpi: Handle pixel clock in firmware
  clk: bcm: rpi: Add support HEVC clock
  clk: bcm2835: fix bcm2835_clock_rate_from_divisor declaration
  clk: bcm2835: Round UART input clock up
  clk: bcm2835: Make peripheral PLLC critical

* clk-vc5:
  clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
  dt-bindings: clock: vc5: Add 5P49V6975
  clk: vc5: Use regmap_{set,clear}_bits() where appropriate
  clk: vc5: Check IO access results

* clk-versaclock:
  clk: Renesas versaclock7 ccf device driver
  dt-bindings: Renesas versaclock7 device tree bindings
 2022-10-04 10:54:34 -07:00
Serge Semin
c0cd3b1790 dt-bindings: clk: baikal-t1: Add DDR/PCIe reset IDs 
Aside with a set of the trigger-like resets Baikal-T1 CCU provides
additional directly controlled reset signals for the DDR and PCIe
controllers. As a preparation before adding these resets support to the
kernel let's extent the Baikal-T1 CCU IDs list with the new IDs, which
will be used to access the corresponding reset controls.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220929225402.9696-7-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2022-09-30 14:19:37 -07:00
AngeloGioacchino Del Regno
f098c088f9 dt-bindings: reset: Add bindings for MT6795 Helio X10 reset controllers 
Add the reset controller bindings for MT6795.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220921091455.41327-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
 2022-09-26 11:13:09 +08:00
AngeloGioacchino Del Regno
697b551e29 dt-bindings: reset: mt8195: Add resets for USB/PCIe t-phy port 1 
Add the reset index for USBSIF P1 (T-PHY port 1), used as either USB
or PCI-Express PHY reset.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220720102817.237483-2-angelogioacchino.delregno@collabora.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2022-08-31 18:16:45 -07:00
AngeloGioacchino Del Regno
7e5073a74f dt-bindings: reset: mt8195: Add resets for PCIE controllers 
Add the reset index for PCIe P0 and P1 (PCIe0, PCIe1) on MT8195.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220629105205.173471-2-angelogioacchino.delregno@collabora.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2022-08-31 18:13:53 -07:00
Linus Torvalds
f7cdaeeab8 power supply and reset changes for the v6.0 series 
power-supply core:
  - none
 
 drivers:
  - pwr-mlxbf: new reset driver for Mellanox BlueField
  - at91-reset: SAMA7G5 support
  - ab8500: continue refurbishing
  - misc. minor fixes
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Merge tag 'for-v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply

Pull power supply and reset updates from Sebastian Reichel:
 "No core patches, only driver updates:

   - pwr-mlxbf: new reset driver for Mellanox BlueField

   - at91-reset: SAMA7G5 support

   - ab8500: continue refurbishing

   - misc minor fixes"

* tag 'for-v6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply: (29 commits)
  power: supply: olpc_battery: Hold the reference returned by of_find_compatible_node
  power: supply: ab8500: add missing destroy_workqueue in ab8500_charger_bind
  power: supply: ab8500: Remove flush_scheduled_work() call.
  power: supply: ab8500_fg: drop duplicated 'is' in comment
  power: supply: ab8500: Drop external charger leftovers
  power: supply: ab8500: Add MAINTAINERS entry
  dt-bindings: power: reset: qcom,pshold: convert to dtschema
  power: supply: Fix typo in power_supply_check_supplies
  power: reset: pwr-mlxbf: change rst_pwr_hid and low_pwr_hid from global to local variables
  power: reset: pwr-mlxbf: add missing include
  power: reset: at91-reset: add support for SAMA7G5
  power: reset: at91-reset: add reset_controller_dev support
  power: reset: at91-reset: add at91_reset_data
  power: reset: at91-reset: document structures and enums
  dt-bindings: reset: add sama7g5 definitions
  dt-bindings: reset: atmel,at91sam9260-reset: add sama7g5 bindings
  dt-bindings: reset: convert Atmel/Microchip reset controller to YAML
  power: reset: pwr-mlxbf: add BlueField SoC power control driver
  power: supply: ab8500: Exit maintenance if too low voltage
  power: supply: ab8500: Respect charge_restart_voltage_uv
  ...
 2022-08-12 09:37:33 -07:00
Linus Torvalds
36001a2fa6 The clk core gains a new set of APIs that allow drivers to both acquire clks 
and prepare and enable them at the same time. This also comes with devm support
 so that drivers can make a single call to get and prepare and enable the clk
 and have that all undone when their driver is removed. Many folks have
 requested this feature over the years, but we've had disagreements about how to
 implement it and if it was worthwhile to encourage drivers to use such an API.
 Now it's here, so let's see how it goes. I hope that by introducing this API we
 can identify drivers that would benefit from further consolidation of clk API
 usage, possibly by moving such logic to the bus layer and out of drivers
 altogether.
 
 Outside of that major API update, we have the usual collection of driver
 updates. A few new SoCs are supported, mostly Qualcomm and Renesas this time
 around. Then we have the long tail of non-critical fixes and minor feature
 additions to various clk drivers. And finally more clk provider migration to
 struct clk_parent_data, reducing boot times in the process.
 
 Core:
  - devm helpers for clk_get() + clk_prepare() and clk_enable()
 
 New Drivers:
  - Support for the camera clock controller in Qualcomm SM8450 and
    the display and gpu clock controllers in Qualcomm SM8350
  - Add support for the Renesas RZ/Five SoC
 
 Updates:
  - Various fixes, new clocks and USB GDSCs are introduced for Qualcomm IPQ8074
  - Fixes to Qualcomm MSM8939 for issues introduced by inheriting the MSM8916
    GCC driver
  - Support for a new type of voteable GDSCs used by Qualcomm SC8280XP PCIe
    GDSCs
  - Qualcomm SC8280XP pipe clocks transitioned to the new phy-mux implementation
  - Qualcomm MSM8996 GCC, RPM clock driver and some clocks in MSM8994 GCC are
    migrated to use clk_parent_data
  - Corrected the topology for Titan (camera) GDSCs on Qualcomm SDM845 and
    SM8250
  - Qualcomm MSM8916 gains more possible frequencies for its GP clocks.
  - The GCC and tsens handling on Qualcomm MSM8960 is reworked to mimic the
    design in IPQ8074 to allow the GCC driver to probe earlier.
  - The regulator based mmcx supply for Qualcomm dispcc and videocc is dropped,
    as the only upstream target that adapted this interface was transitioned
    several kernel versions ago
  - Qualcomm GDSCs found to be enabled at boot will now reflect in the enable
    count of the supply, as was done with the regulator supplies previously
  - Correct adc1, nic_media and edma1's parents for NXP i.MX93
  - rdiv, mfd values, the return rate in recalc_rate and add more frequencies in
    the table for fracn-gppll on i.MX
  - Remove Allwinner workaround logic/compatible in fixed factor code
  - MediaTek clk driver cleanups
  - Add reset support to more MediaTek clk drivers
  - deduplicate Allwinner ccu_clks arrays
  - Allwinner H6 GPU DFS support
  - Adjust Allwinner Kconfig to limit choice
  - Fix initconst confusion on Renesas R-Car Gen4
  - Add GPT/POEG (PWM) clocks and resets on Renesas RZ/G2L
  - Add PFC and WDT clocks and resets on Renesas RZ/V2M
  - Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on
    Renesas R-Car S4-8
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The clk core gains a new set of APIs that allow drivers to both
  acquire clks and prepare and enable them at the same time. This also
  comes with devm support so that drivers can make a single call to get
  and prepare and enable the clk and have that all undone when their
  driver is removed.

  Many folks have requested this feature over the years, but we've had
  disagreements about how to implement it and if it was worthwhile to
  encourage drivers to use such an API.

  Now it's here, so let's see how it goes.

  I hope that by introducing this API we can identify drivers that would
  benefit from further consolidation of clk API usage, possibly by
  moving such logic to the bus layer and out of drivers altogether.

  Outside of that major API update, we have the usual collection of
  driver updates. A few new SoCs are supported, mostly Qualcomm and
  Renesas this time around. Then we have the long tail of non-critical
  fixes and minor feature additions to various clk drivers.

  And finally more clk provider migration to struct clk_parent_data,
  reducing boot times in the process.

  Summary:

  Core:

   - devm helpers for clk_get() + clk_prepare() and clk_enable()

  New Drivers:

   - Support for the camera clock controller in Qualcomm SM8450 and the
     display and gpu clock controllers in Qualcomm SM8350

   - Add support for the Renesas RZ/Five SoC

  Updates:

   - Various fixes, new clocks and USB GDSCs are introduced for Qualcomm
     IPQ8074

   - Fixes to Qualcomm MSM8939 for issues introduced by inheriting the
     MSM8916 GCC driver

   - Support for a new type of voteable GDSCs used by Qualcomm SC8280XP
     PCIe GDSCs

   - Qualcomm SC8280XP pipe clocks transitioned to the new phy-mux
     implementation

   - Qualcomm MSM8996 GCC, RPM clock driver and some clocks in MSM8994
     GCC are migrated to use clk_parent_data

   - Corrected the topology for Titan (camera) GDSCs on Qualcomm SDM845
     and SM8250

   - Qualcomm MSM8916 gains more possible frequencies for its GP clocks.

   - The GCC and tsens handling on Qualcomm MSM8960 is reworked to mimic
     the design in IPQ8074 to allow the GCC driver to probe earlier.

   - The regulator based mmcx supply for Qualcomm dispcc and videocc is
     dropped, as the only upstream target that adapted this interface
     was transitioned several kernel versions ago

   - Qualcomm GDSCs found to be enabled at boot will now reflect in the
     enable count of the supply, as was done with the regulator supplies
     previously

   - Correct adc1, nic_media and edma1's parents for NXP i.MX93

   - rdiv, mfd values, the return rate in recalc_rate and add more
     frequencies in the table for fracn-gppll on i.MX

   - Remove Allwinner workaround logic/compatible in fixed factor code

   - MediaTek clk driver cleanups

   - Add reset support to more MediaTek clk drivers

   - deduplicate Allwinner ccu_clks arrays

   - Allwinner H6 GPU DFS support

   - Adjust Allwinner Kconfig to limit choice

   - Fix initconst confusion on Renesas R-Car Gen4

   - Add GPT/POEG (PWM) clocks and resets on Renesas RZ/G2L

   - Add PFC and WDT clocks and resets on Renesas RZ/V2M

   - Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on
     Renesas R-Car S4-8"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (124 commits)
  clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw()
  clk: mux: Introduce devm_clk_hw_register_mux_parent_hws()
  clk: divider: Introduce devm_clk_hw_register_divider_parent_hw()
  clk: qcom: gcc-msm8994: use parent_hws for gpll0/4
  clk: qcom: clk-rpm: convert to parent_data API
  dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc
  clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies
  clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies
  clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies
  clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions
  clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock
  clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk
  clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled
  clk: qcom: Drop mmcx gdsc supply for dispcc and videocc
  clk: qcom: fix build error initializer element is not constant
  clk: sprd: Add dt-bindings include file for UMS512
  dt-bindings: clk: sprd: Add bindings for ums512 clock controller
  clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS
  dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources
  clk: qcom: add support for SM8350 DISPCC
  ...
 2022-08-04 18:40:08 -07:00
Linus Torvalds
dd65b96492 ARM: new SoC support for 6.0 
This adds initial support for two SoC families that have been under
 review for a while. In both cases, the origonal idea was to have a
 minimally functional version, but we ended up leaving out the clk drivers
 that are still under review and will be merged through the corresponding
 subsystem tree.
 
 The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and
 based on the 32-bit NPCM7xx family but is now getting added to
 arch/arm64 as well.
 
 Sunplus SP7021, also known as Plus1, is a general-purpose
 System-in-Package design based on the 32-bit Cortex-A7 SoC
 on the main chip, plus an I/O chip and memory in the same
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Merge tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM new SoC support from Arnd Bergmann:
 "This adds initial support for two SoC families that have been under
  review for a while. In both cases, the origonal idea was to have a
  minimally functional version, but we ended up leaving out the clk
  drivers that are still under review and will be merged through the
  corresponding subsystem tree.

  The Nuvoton NPCM8xx is a 64-bit Baseboard Management Controller and
  based on the 32-bit NPCM7xx family but is now getting added to
  arch/arm64 as well.

  Sunplus SP7021, also known as Plus1, is a general-purpose
  System-in-Package design based on the 32-bit Cortex-A7 SoC on the main
  chip, plus an I/O chip and memory in the same"

* tag 'arm-newsoc-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
  MAINTAINERS: rectify entry for ARM/NUVOTON NPCM ARCHITECTURE
  arm64: defconfig: Add Nuvoton NPCM family support
  arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
  arm64: dts: nuvoton: Add initial NPCM8XX device tree
  arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
  dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
  dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
  dt-bindings: arm: npcm: Add maintainer
  reset: npcm: Add NPCM8XX support
  dt-bindings: reset: npcm: Add support for NPCM8XX
  reset: npcm: using syscon instead of device data
  ARM: dts: nuvoton: add reset syscon property
  dt-bindings: reset: npcm: add GCR syscon property
  dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
  dt-bindings: watchdog: npcm: Add npcm845 compatible string
  dt-bindings: timer: npcm: Add npcm845 compatible string
  ARM: dts: Add Sunplus SP7021-Demo-V3 board device tree
  ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig
  ARM: sunplus: Add initial support for Sunplus SP7021 SoC
  irqchip: Add Sunplus SP7021 interrupt controller driver
  ...
 2022-08-02 08:29:18 -07:00
Mikko Perttunen
63a6ef2360 dt-bindings: Add headers for Host1x and VIC on Tegra234 
Add clock, memory controller, powergate and reset dt-binding headers
for Host1x and VIC on Tegra234.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2022-07-08 16:17:04 +02:00
Qin Jian
55bfc376b8 dt-bindings: reset: Add bindings for SP7021 reset driver 
Add documentation to describe Sunplus SP7021 reset driver bindings.

Signed-off-by: Qin Jian <qinjian@cqplus1.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-07-08 14:23:39 +02:00
Thierry Reding
b0aedf342b dt-bindings: Add Tegra234 MGBE clocks and resets 
Add the clocks and resets used by the MGBE Ethernet hardware found on
Tegra234 SoCs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2022-07-08 10:20:59 +02:00
Claudiu Beznea
5994f58977 dt-bindings: reset: add sama7g5 definitions 
Add reset bindings for SAMA7G5. At the moment only USB PHYs are
included.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 2022-06-17 17:20:00 +02:00
Rex-BC Chen
5ea61b478f dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 
To support reset of infra_ao, add the index of infra_ao reset of
thermal/svs for MT8186.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-18-rex-bc.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2022-06-15 17:24:25 -07:00
Rex-BC Chen
fb91526b5f dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195 
To support reset of infra_ao, add the index of infra_ao reset of
thermal/svs/pcei for MT8192 and thermal/svs for MT8195.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
[Nícolas: Test for MT8192]
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-14-rex-bc.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2022-06-15 17:24:13 -07:00
Akhil R
3ffb20f5c7 dt-bindings: Add headers for Tegra234 GPCDMA 
Add reset and IOMMU header for Tegra234 GPCDMA

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2022-06-08 15:50:24 +02:00
Linus Torvalds
96752be4d7 linux-watchdog 5.19-rc1 tag 
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Merge tag 'linux-watchdog-5.19-rc1' of git://www.linux-watchdog.org/linux-watchdog

Pull watchdog updates from Wim Van Sebroeck:

 - Add MediaTek MT8186 support

 - Add Mediatek MT7986 reset-controller support

 - Add i.MX93 support

 - Add watchdog driver for Sunplus SP7021

 - Add SC8180X and SC8280XP compatibles

 - Add Renesas RZ/N1 Watchdog driver and support for RZ/N1

 - rzg2l_wdt improvements and fixes

 - Several other improvements and fixes

* tag 'linux-watchdog-5.19-rc1' of git://www.linux-watchdog.org/linux-watchdog: (38 commits)
  watchdog: ts4800_wdt: Fix refcount leak in ts4800_wdt_probe
  dt-bindings: watchdog: renesas,wdt: R-Car V3U is R-Car Gen4
  watchdog: Add Renesas RZ/N1 Watchdog driver
  dt-bindings: watchdog: renesas,wdt: Add support for RZ/N1
  watchdog: wdat_wdt: Stop watchdog when uninstalling module
  watchdog: wdat_wdt: Stop watchdog when rebooting the system
  watchdog: wdat_wdt: Using the existing function to check parameter timeout
  dt-bindings: watchdog: da9062: add watchdog timeout mode
  dt-bindings: watchdog: renesas,wdt: Document RZ/G2UL SoC
  watchdog: iTCO_wdt: Using existing macro define covers more scenarios
  watchdog: rti-wdt: Fix pm_runtime_get_sync() error checking
  dt-bindings: watchdog: Add SC8180X and SC8280XP compatibles
  watchdog: rti_wdt: Fix calculation and evaluation of preset heartbeat
  dt-bindings: watchdog: uniphier: Use unevaluatedProperties
  watchdog: sp805: disable watchdog on remove
  watchdog: da9063: optionally disable watchdog during suspend
  dt-bindings: mfd: da9063: watchdog: add suspend disable option
  dt-bindings: watchdog: sunxi: clarify clock support
  dt-bindings: watchdog: sunxi: fix F1C100s compatible
  watchdog: Add watchdog driver for Sunplus SP7021
  ...
 2022-06-01 14:05:16 -07:00
Linus Torvalds
6b0e34a030 Mainly driver updates this time around. There's a single patch to the core clk 
framework that simplifies a runtime PM call. Otherwise the majority of the diff
 falls to a few SoC drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some
 new hardware support and what comes along with that is quite a few lines of
 data and some clk_ops code. Beyond the new hardware support we have the usual
 pile of driver updates that add missing clks on already supported SoCs or fix
 up problems like bad clk tree descriptions. It's nice to see that more drivers
 are moving to clk_hw based APIs too.
 
 New Drivers:
  - Add STM32MP13 RCC driver (Reset Clock Controller)
  - MediaTek MT8186 SoC clk support
  - Airoha EN7523 SoC system clocks
  - Clock driver for exynosautov9 SoC
  - Renesas R-Car V4H and RZ/V2M SoCs
  - Renesas RZ/G2UL SoC
  - LPASS clk driver for Qualcomm sc7280 SoC
  - GCC clk driver for Qualcomm SC8280XP SoC
 
 Updates:
  - SDCC uses floor clk ops on Qualcomm MSM8976
  - Add modem reset and fix RPM clks on Qualcomm MSM8976
  - Add the two missing CLKOUT clocks for U8500/DB8500 SoC
  - Mark some clks critical on Ingenic X1000
  - Convert ux500 to clk_hw
  - Move MediaTek driver to clk_hw provider APIs
  - Use i2c driver probe_new to avoid id scans
  - Convert a number of Rockchip dt bindings to YAML
  - Mark hclk_vo critical on Rockchip rk3568
  - Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
  - Various cleanups like memory allocation error checks and plugged leaks
  - Allwinner H6 RTC clock support
  - Allwinner H616 32 kHz clock support
  - Add the Universal Flash Storage clock on Renesas R-Car S4-8
  - Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
    I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas RZ/G2UL
  - Add display clock support on Renesas RZ/G2L
  - Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
  - Add 27 MHz phy PLL ref clock on i.MX
  - Add mcore_booted module parameter to tell kernel M core has already booted
    for i.MX
  - Remove snvs clock on i.MX because it was for secure world only
  - Add dt bindings for i.MX8MN GPT
  - Add DISP2 pixel clock for i.MX8MP
  - Add clkout1/2 for i.MX8MP
  - Fix parent clock of ubs_root_clk for i.MX8MP
  - Implement better RCG parking on Qualcomm SoCs using the shared RCG clk ops
  - Kerneldoc fixes
  - Switch Tegra BPMP to determine_rate clk op
  - Add a pointer to dt schema for generic clock bindings
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Mainly driver updates this time around.

  There's a single patch to the core clk framework that simplifies a
  runtime PM call. Otherwise the majority of the diff falls to a few SoC
  drivers: Qualcomm, STM32 and MediaTek. Those SoCs gain some new
  hardware support and what comes along with that is quite a few lines
  of data and some clk_ops code.

  Beyond the new hardware support we have the usual pile of driver
  updates that add missing clks on already supported SoCs or fix up
  problems like bad clk tree descriptions. It's nice to see that more
  drivers are moving to clk_hw based APIs too.

  New Drivers:
   - Add STM32MP13 RCC driver (Reset Clock Controller)
   - MediaTek MT8186 SoC clk support
   - Airoha EN7523 SoC system clocks
   - Clock driver for exynosautov9 SoC
   - Renesas R-Car V4H and RZ/V2M SoCs
   - Renesas RZ/G2UL SoC
   - LPASS clk driver for Qualcomm sc7280 SoC
   - GCC clk driver for Qualcomm SC8280XP SoC

  Updates:
   - SDCC uses floor clk ops on Qualcomm MSM8976
   - Add modem reset and fix RPM clks on Qualcomm MSM8976
   - Add the two missing CLKOUT clocks for U8500/DB8500 SoC
   - Mark some clks critical on Ingenic X1000
   - Convert ux500 to clk_hw
   - Move MediaTek driver to clk_hw provider APIs
   - Use i2c driver probe_new to avoid id scans
   - Convert a number of Rockchip dt bindings to YAML
   - Mark hclk_vo critical on Rockchip rk3568
   - Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage
   - Various cleanups like memory allocation error checks and plugged
     leaks
   - Allwinner H6 RTC clock support
   - Allwinner H616 32 kHz clock support
   - Add the Universal Flash Storage clock on Renesas R-Car S4-8
   - Add I2C, SSIF-2 (sound), USB, CANFD, OSTM (timer), WDT, SPI Multi
     I/O Bus, RSPI, TSU (thermal), and ADC clocks and resets on Renesas
     RZ/G2UL
   - Add display clock support on Renesas RZ/G2L
   - Add RPC (QSPI/HyperFlash) clocks on Renesas R-Car E3 and D3
   - Add 27 MHz phy PLL ref clock on i.MX
   - Add mcore_booted module parameter to tell kernel M core has already
     booted for i.MX
   - Remove snvs clock on i.MX because it was for secure world only
   - Add dt bindings for i.MX8MN GPT
   - Add DISP2 pixel clock for i.MX8MP
   - Add clkout1/2 for i.MX8MP
   - Fix parent clock of ubs_root_clk for i.MX8MP
   - Implement better RCG parking on Qualcomm SoCs using the shared RCG
     clk ops
   - Kerneldoc fixes
   - Switch Tegra BPMP to determine_rate clk op
   - Add a pointer to dt schema for generic clock bindings"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (168 commits)
  Revert "clk: qcom: regmap-mux: add pipe clk implementation"
  Revert "clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
  Revert "clk: qcom: gcc-sm8450: use new clk_regmap_mux_safe_ops for PCIe pipe clocks"
  clk: bcm: rpi: Use correct order for the parameters of devm_kcalloc()
  clk: stm32mp13: add safe mux management
  clk: stm32mp13: add multi mux function
  clk: stm32mp13: add all STM32MP13 kernel clocks
  clk: stm32mp13: add all STM32MP13 peripheral clocks
  clk: stm32mp13: manage secured clocks
  clk: stm32mp13: add composite clock
  clk: stm32mp13: add stm32 divider clock
  clk: stm32mp13: add stm32_gate management
  clk: stm32mp13: add stm32_mux clock management
  clk: stm32: Introduce STM32MP13 RCC drivers (Reset Clock Controller)
  dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC
  clk: ti: clkctrl: replace usage of found with dedicated list iterator variable
  clk: ti: composite: Prefer kcalloc over open coded arithmetic
  dt-bindings: clock: exynosautov9: correct count of NR_CLK
  clk: mediatek: mt8173: Switch to clk_hw provider APIs
  clk: mediatek: Switch to clk_hw provider APIs
  ...
 2022-05-27 15:33:24 -07:00
Linus Torvalds
cc3c470ae4 ARM: driver changes for 5.19 
There are minor updates to SoC specific drivers for chips by Rockchip,
 Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom. Noteworthy
 driver changes include:
 
 - Several conversions of DT bindings to yaml format.
 
 - Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.
 
 - Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
   and support for more chips in the RPMh power domains and the soc-id.
 
 - NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.
 
 - Apple M1 gains support for the on-chip NVMe controller, making it
   possible to finally use the internal disks. This also includes SoC
   drivers for their RTKit IPC and for the SART DMA address filter.
 
 For other subsystems that merge their drivers through the SoC tree,
 we have
 
 - Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
   SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
   now has a cache for firmware argument structures as an optimization,
   and SCMI now supports the 3.1 version of the specification.
 
 - Reset controller updates to Amlogic, ASpeed, Renesas and ACPI drivers
 
 - Memory controller updates for Tegra, and a few updates for other
   platforms.
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Merge tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM driver updates from Arnd Bergmann:
 "There are minor updates to SoC specific drivers for chips by Rockchip,
  Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom.

  Noteworthy driver changes include:

   - Several conversions of DT bindings to yaml format.

   - Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs.

   - Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core),
     and support for more chips in the RPMh power domains and the
     soc-id.

   - NXP has a new driver for the HDMI blk-ctrl on i.MX8MP.

   - Apple M1 gains support for the on-chip NVMe controller, making it
     possible to finally use the internal disks. This also includes SoC
     drivers for their RTKit IPC and for the SART DMA address filter.

  For other subsystems that merge their drivers through the SoC tree, we
  have

   - Firmware drivers for the ARM firmware stack including TEE, OP-TEE,
     SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE
     now has a cache for firmware argument structures as an
     optimization, and SCMI now supports the 3.1 version of the
     specification.

   - Reset controller updates to Amlogic, ASpeed, Renesas and ACPI
     drivers

   - Memory controller updates for Tegra, and a few updates for other
     platforms"

* tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits)
  memory: tegra: Add MC error logging on Tegra186 onward
  memory: tegra: Add memory controller channels support
  memory: tegra: Add APE memory clients for Tegra234
  memory: tegra: Add Tegra234 support
  nvme-apple: fix sparse endianess warnings
  soc/tegra: pmc: Document core domain fields
  soc: qcom: pdr: use static for servreg_* variables
  soc: imx: fix semicolon.cocci warnings
  soc: renesas: R-Car V3U is R-Car Gen4
  soc: imx: add i.MX8MP HDMI blk-ctrl
  soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
  soc: imx: add i.MX8MP HSIO blk-ctrl
  soc: imx: imx8m-blk-ctrl: set power device name
  soc: qcom: llcc: Add sc8180x and sc8280xp configurations
  dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles
  soc/tegra: pmc: Select REGMAP
  dt-bindings: reset: st,sti-powerdown: Convert to yaml
  dt-bindings: reset: st,sti-picophyreset: Convert to yaml
  dt-bindings: reset: socfpga: Convert to yaml
  dt-bindings: reset: snps,axs10x-reset: Convert to yaml
  ...
 2022-05-26 10:32:47 -07:00
Gabriel Fernandez
722dc8a1d5 dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC 
New compatible to manage clock and reset of STM32MP13 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Link: https://lore.kernel.org/r/20220516070600.7692-2-gabriel.fernandez@foss.st.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2022-05-20 21:07:48 -07:00
Arnd Bergmann
82706d6fb1 MT8195: 
- add evaluation and demo board
 
 MT8192:
 - add new nodes: pwrap, PMIC, scp, USB, efuse, IOMMU, smi, DPI, PCIe,
   SPMI, audio system, MMC and video enconder
 - add evaluation board
 
 MT8183:
 - fix dtschema issues
 - update compatible for the display ambient light processor (disp-aal)
 - fix dtschema warning for the pumpki board
 
 MT8173:
 - add power domains to the video enconder nodes
 - add GCE support to the display mutex node
 
 MT7622:
 - specify number of DMA requests explicitely
 - specify level 2 cache topology
 - add SPI-NAND flash device
 - fix dtschema warnings for the System Companion Processor (SCP)
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Merge tag 'v5.18-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

MT8195:
- add evaluation and demo board

MT8192:
- add new nodes: pwrap, PMIC, scp, USB, efuse, IOMMU, smi, DPI, PCIe,
  SPMI, audio system, MMC and video enconder
- add evaluation board

MT8183:
- fix dtschema issues
- update compatible for the display ambient light processor (disp-aal)
- fix dtschema warning for the pumpki board

MT8173:
- add power domains to the video enconder nodes
- add GCE support to the display mutex node

MT7622:
- specify number of DMA requests explicitely
- specify level 2 cache topology
- add SPI-NAND flash device
- fix dtschema warnings for the System Companion Processor (SCP)

* tag 'v5.18-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (37 commits)
  arm64: dts: mt8192: Follow binding order for SCP registers
  arm64: dts: mediatek: add mtk-snfi for mt7622
  arm64: dts: mediatek: mt8195-demo: enable uart1
  arm64: dts: mediatek: mt8195-demo: Remove input-name property
  arm64: dts: mediatek: mt8183-pumpkin: fix bad thermistor node name
  arm64: dts: mt7622: specify the L2 cache topology
  arm64: dts: mt7622: specify the number of DMA requests
  arm64: dts: mediatek: pumpkin: Remove input-name property
  arm64: dts: mediatek: mt8173: Add gce-client-reg handle to disp-mutex
  arm64: dts: mediatek: Add device-tree for MT8195 Demo board
  dt-bindings: arm64: dts: mediatek: Add mt8195-demo board
  arm64: dts: Add mediatek SoC mt8195 and evaluation board
  arm64: dts: mt8192: Add mmc device nodes
  arm64: dts: mt8183: Update disp_aal node compatible
  arm64: dts: mt8192: Add audio-related nodes
  arm64: dts: mt8192: Add spmi node
  dt-bindings: arm: Add compatible for Mediatek MT8192
  arm64: dts: mt6359: add PMIC MT6359 related nodes
  arm64: dts: mediatek: mt8173: Add power domain to encoder nodes
  arm64: dts: mediatek: Get rid of mediatek, larb for MM nodes
  ...

Link: https://lore.kernel.org/r/2cd90ca7-7541-d47a-fec6-b0c64cf74fa3@gmail.com

Like the 32-bit branch, this contains an incompatible binding change
by removing the mediatek,larb properties from the dts files, so these
no longer work with kernels prior to 5.18.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-05-13 23:26:21 +02:00
Sam Shih
5794dda109 dt-bindings: reset: mt7986: Add reset-controller header file 
Add infracfg, toprgu, and ethsys reset-controller header file
for MT7986 platform.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220105100456.7126-2-sam.shih@mediatek.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
 2022-05-08 10:34:04 +02:00
Runyang Chen
1d6866e8f1 dt-bindings: reset: mt8186: add reset-controller header file 
1. Add toprgu reset-controller header file for MT8186.
2. Add DSI software reset bit which is controlled in MMSYS for MT8186.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220301054405.25021-3-rex-bc.chen@mediatek.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
 2022-05-08 10:33:58 +02:00
Arnd Bergmann
1bc44c1e79 arm64: tegra: Device tree changes for v5.19-rc1 
This adds some improvements on Tegra234 (QSPI, CCPLEX), improves the
 SDMMC clock speed on Tegra194 and adds the ASRC audio block on various
 chip generations. Memory controller channels are also added on Tegra186
 and later and the missing DFLL reset is added for Tegra210.
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Merge tag 'tegra-for-5.19-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.19-rc1

This adds some improvements on Tegra234 (QSPI, CCPLEX), improves the
SDMMC clock speed on Tegra194 and adds the ASRC audio block on various
chip generations. Memory controller channels are also added on Tegra186
and later and the missing DFLL reset is added for Tegra210.

* tag 'tegra-for-5.19-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Add missing DFLL reset on Tegra210
  arm64: tegra: Add memory controller channels
  arm64: tegra: Enable ASRC on various platforms
  arm64: tegra: Add ASRC device on Tegra186 and later
  arm64: tegra: Update PWM fan node name
  arm64: tegra: Add node for Tegra234 CCPLEX cluster
  arm64: tegra: Add QSPI controllers on Tegra234
  arm64: tegra: Update SDMMC1/3 clock source for Tegra194

Link: https://lore.kernel.org/r/20220506143005.3916655-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2022-05-06 22:39:39 +02:00
Alexandre Torgue
5f5d7decf0 dt-bindings: reset: stm32mp15: rename RST_SCMI define 
As we only have one SCMI instance, it's not necessary to add an index to
the name.

Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Rob Herring <robh@kernel.org>
 2022-05-04 11:00:56 +02:00
Zelong Dong
52f988d757 dt-bindings: reset: add bindings for the Meson-S4 SoC Reset Controller 
Add DT bindings for the Meson-S4 SoC Reset Controller include file.

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20220107023931.13251-3-zelong.dong@amlogic.com
 2022-05-03 17:40:51 +02:00
Ashish Singhal
71f69ffa01 arm64: tegra: Add QSPI controllers on Tegra234 
This adds the QSPI controllers on the Tegra234 SoC and populates the
SPI NOR flash device for the Jetson AGX Orin platform.

Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2022-04-06 15:27:17 +02:00
Allen-KH Cheng
19c66219e4 arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0 
Reset the DSI hardware is needed to prevent different settings between
the bootloader and the kernel.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220318144534.17996-20-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
 2022-04-04 14:09:37 +02:00
Linus Torvalds
9512433987 There's one large change in the core clk framework here. We change how 
clk_set_rate_range() works so that the frequency is re-evaulated each time the
 rate is changed. Previously we wouldn't let clk providers see a rate that was
 different if it was still within the range, which could be bad for power if the
 clk could run slower when a range expands. Now the clk provider can decide to
 do something differently when the constraints change. This broke Nvidia's clk
 driver so we had to wait for the fix for that to bake a little more in -next.
 
 The rate range patch series also introduced a kunit suite for the clk framework
 that we're going to extend in the next release. It already made it easy to find
 corner cases in the rate range patches so I'm excited to see it cover more clk
 code and increase our confidence in core framework patches in the future. I
 also added a kunit test for the basic clk gate code and that work will continue
 to cover more basic clk types: muxes, dividers, etc.
 
 Beyond the core code we have the usual set of clk driver updates and additions.
 Qualcomm again dominates the diffstat here with lots more SoCs being supported
 and i.MX follows afer that with a similar number of SoCs gaining clk drivers.
 Beyond those large additions there's drivers being modernized to use
 clk_parent_data so we can move away from global string names for all the clks
 in an SoC. Finally there's lots of little fixes all over the clk drivers for
 typos, warnings, and missing clks that aren't critical and get batched up
 waiting for the next merge window to open. Nothing super big stands out in the
 driver pile. Full details are below.
 
 Core:
  - Make clk_set_rate_range() re-evaluate the limits each time
  - Introduce various clk_set_rate_range() tests
  - Add clk_drop_range() to drop a previously set range
 
 New Drivers:
  - i.MXRT1050 clock driver and bindings
  - i.MX8DXL clock driver and bindings
  - i.MX93 clock driver and bindings
  - NCO blocks on Apple SoCs
  - Audio clks on StarFive JH7100 RISC-V SoC
  - Add support for the new Renesas RZ/V2L SoC
  - Qualcomm SDX65 A7 PLL
  - Qualcomm SM6350 GPU clks
  - Qualcomm SM6125, SM6350, QCS2290 display clks
  - Qualcomm MSM8226 multimedia clks
 
 Updates:
  - Kunit tests for clk-gate implementation
  - Terminate arrays with sentinels and make that clearer
  - Cleanup SPDX tags
  - Fix typos in comments
  - Mark mux table as const in clk-mux
  - Make the all_lists array const
  - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add
    support for dynamic mode
  - Clock configuration on Microchip PolarFire SoCs
  - Free allocations on probe error in Mediatek clk driver
  - Modernize Mediatek clk driver by consolidating code
  - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on
    Renesas R-Car S4-8
  - Improve the clocks for the Rockchip rk3568 display outputs (parenting, pll-rates)
  - Use of_device_get_match_data() instead of open-coding on Rockchip rk3568
  - Reintroduce the expected fractional-divider behaviour that disappeared
    with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
  - Remove SYS PLL 1/2 clock gates for i.MX8M*
  - Remove AUDIO MCLK ROOT from i.MX7D
  - Add fracn gppll clock type used by i.MX93
  - Add new composite clock for i.MX93
  - Add missing media mipi phy ref clock for i.MX8MP
  - Fix off by one in imx_lpcg_parse_clks_from_dt()
  - Rework for the imx pll14xx
  - sama7g5: One low priority fix for GCLK of PDMC
  - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
  - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
  - Add CAN-FD clocks on Renesas R-Car V3U
  - Qualcomm SC8280XP RPMCC
  - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs
  - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to YAML
  - Convert various Qualcomm drivers to use clk_parent_data
  - Remove test clocks from various Qualcomm drivers
  - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS
  - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs
  - Better pixel clk frequency support on Qualcomm RCG2 clks
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "There's one large change in the core clk framework here. We change how
  clk_set_rate_range() works so that the frequency is re-evaulated each
  time the rate is changed. Previously we wouldn't let clk providers see
  a rate that was different if it was still within the range, which
  could be bad for power if the clk could run slower when a range
  expands. Now the clk provider can decide to do something differently
  when the constraints change. This broke Nvidia's clk driver so we had
  to wait for the fix for that to bake a little more in -next.

  The rate range patch series also introduced a kunit suite for the clk
  framework that we're going to extend in the next release. It already
  made it easy to find corner cases in the rate range patches so I'm
  excited to see it cover more clk code and increase our confidence in
  core framework patches in the future. I also added a kunit test for
  the basic clk gate code and that work will continue to cover more
  basic clk types: muxes, dividers, etc.

  Beyond the core code we have the usual set of clk driver updates and
  additions. Qualcomm again dominates the diffstat here with lots more
  SoCs being supported and i.MX follows afer that with a similar number
  of SoCs gaining clk drivers. Beyond those large additions there's
  drivers being modernized to use clk_parent_data so we can move away
  from global string names for all the clks in an SoC. Finally there's
  lots of little fixes all over the clk drivers for typos, warnings, and
  missing clks that aren't critical and get batched up waiting for the
  next merge window to open. Nothing super big stands out in the driver
  pile. Full details are below.

  Core:
   - Make clk_set_rate_range() re-evaluate the limits each time
   - Introduce various clk_set_rate_range() tests
   - Add clk_drop_range() to drop a previously set range

  New Drivers:
   - i.MXRT1050 clock driver and bindings
   - i.MX8DXL clock driver and bindings
   - i.MX93 clock driver and bindings
   - NCO blocks on Apple SoCs
   - Audio clks on StarFive JH7100 RISC-V SoC
   - Add support for the new Renesas RZ/V2L SoC
   - Qualcomm SDX65 A7 PLL
   - Qualcomm SM6350 GPU clks
   - Qualcomm SM6125, SM6350, QCS2290 display clks
   - Qualcomm MSM8226 multimedia clks

  Updates:
   - Kunit tests for clk-gate implementation
   - Terminate arrays with sentinels and make that clearer
   - Cleanup SPDX tags
   - Fix typos in comments
   - Mark mux table as const in clk-mux
   - Make the all_lists array const
   - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding
     and add support for dynamic mode
   - Clock configuration on Microchip PolarFire SoCs
   - Free allocations on probe error in Mediatek clk driver
   - Modernize Mediatek clk driver by consolidating code
   - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks
     on Renesas R-Car S4-8
   - Improve the clocks for the Rockchip rk3568 display outputs
     (parenting, pll-rates)
   - Use of_device_get_match_data() instead of open-coding on Rockchip
     rk3568
   - Reintroduce the expected fractional-divider behaviour that
     disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS
   - Remove SYS PLL 1/2 clock gates for i.MX8M*
   - Remove AUDIO MCLK ROOT from i.MX7D
   - Add fracn gppll clock type used by i.MX93
   - Add new composite clock for i.MX93
   - Add missing media mipi phy ref clock for i.MX8MP
   - Fix off by one in imx_lpcg_parse_clks_from_dt()
   - Rework for the imx pll14xx
   - sama7g5: One low priority fix for GCLK of PDMC
   - Add DMA engine (SYS-DMAC) clocks on Renesas R-Car S4-8
   - Add MOST (MediaLB I/F) clocks on Renesas R-Car E3 and D3
   - Add CAN-FD clocks on Renesas R-Car V3U
   - Qualcomm SC8280XP RPMCC
   - Add some missing clks on Qualcomm MSM8992/MSM8994/MSM8998 SoCs
   - Rework Qualcomm GCC bindings and convert SDM845 camera bindig to
     YAML
   - Convert various Qualcomm drivers to use clk_parent_data
   - Remove test clocks from various Qualcomm drivers
   - Crypto engine clks on Qualcomm IPQ806x + more freqs for SDCC/NSS
   - Qualcomm SM8150 EMAC, PCIe, UFS GDSCs
   - Better pixel clk frequency support on Qualcomm RCG2 clks"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits)
  clk: zynq: Update the parameters to zynq_clk_register_periph_clk
  clk: zynq: trivial warning fix
  clk: Drop the rate range on clk_put()
  clk: test: Test clk_set_rate_range on orphan mux
  clk: Initialize orphan req_rate
  dt-bindings: clock: drop useless consumer example
  dt-bindings: clock: renesas: Make example 'clocks' parsable
  clk: qcom: gcc-msm8994: Fix gpll4 width
  dt-bindings: clock: fix dt_binding_check error for qcom,gcc-other.yaml
  clk: rs9: Add Renesas 9-series PCIe clock generator driver
  clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index()
  clk: visconti: prevent array overflow in visconti_clk_register_gates()
  dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator
  clk: sifive: Move all stuff into SoCs header files from C files
  clk: sifive: Add SoCs prefix in each SoCs-dependent data
  riscv: dts: Change the macro name of prci in each device node
  dt-bindings: change the macro name of prci in header files and example
  clk: sifive: duplicate the macro definitions for the time being
  clk: qcom: sm6125-gcc: fix typos in comments
  clk: ti: clkctrl: fix typos in comments
  ...
 2022-03-30 10:11:04 -07:00
Linus Torvalds
dfdc1de642 Staging driver update for 5.18-rc1 
Here is the big set of staging driver updates for 5.18-rc1.
 
 Loads of tiny cleanups for almost all staging drivers in here, nothing
 major at all.  Highlights include:
 	- remove the ashmem Android driver.  It is long-dead and if
 	  there are any legacy userspace applications still using it,
 	  the Android kernel images will maintain it, the community
 	  shouldn't care about it anymore
 	- wfx wifi driver major cleanups.  Should be ready to merge out
 	  of staging soon, and will coordinate with the wifi maintainers
 	  after -rc1 is out
 	- major cleanups and unwinding of the layers of the r8188eu
 	  driver.  It's amazing just how many unneeded layers of
 	  abstraction is in there, just when we think it's done, another
 	  is found...
 	- lots of tiny coding style cleanups in many other staging
 	  drivers.
 
 There will be merge conflict with a fbtft change and the spi driver
 changes in your tree, but it's pretty obvious what to do (the function
 shouldn't return anything.)
 
 All have been in linux-next for a while with no reported problems.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'staging-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging driver updates from Greg KH:
 "Here is the big set of staging driver updates for 5.18-rc1.

  Loads of tiny cleanups for almost all staging drivers in here, nothing
  major at all. Highlights include:

   - remove the ashmem Android driver. It is long-dead and if there are
     any legacy userspace applications still using it, the Android
     kernel images will maintain it, the community shouldn't care about
     it anymore

   - wfx wifi driver major cleanups. Should be ready to merge out of
     staging soon, and will coordinate with the wifi maintainers after
     -rc1 is out

   - major cleanups and unwinding of the layers of the r8188eu driver.
     It's amazing just how many unneeded layers of abstraction is in
     there, just when we think it's done, another is found...

   - lots of tiny coding style cleanups in many other staging drivers.

  All have been in linux-next for a while with no reported problems"

* tag 'staging-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (455 commits)
  staging: r8188eu: remove unnecessary memset in r8188eu
  staging: greybus: introduce pwm_ops::apply
  staging: rts5208: Resolve checkpatch.pl issues.
  staging: sm750fb: fix naming style
  staging: fbtft: Consider type of init sequence values in fbtft_init_display()
  staging: fbtft: Constify buf parameter in fbtft_dbg_hex()
  staging: mmal-vchiq: clear redundant item named bulk_scratch
  mips: dts: ralink: add MT7621 SoC
  staging: r8188eu: remove some unused local ieee80211 macros
  staging: r8188eu: make rtl8188e_process_phy_info static
  staging: r8188eu: remove unused function prototype
  staging: r8188eu: remove three unused receive defines
  staging: r8188eu: remove unnecessary initializations
  staging: rtl8192e: Fix spelling mistake "RESQUEST" -> "REQUEST"
  MAINTAINERS: remove the obsolete file entry for staging in ANDROID DRIVERS
  staging: r8188eu: proper error handling in rtw_init_drv_sw
  staging: r8188eu: call _cancel_timer_ex from _rtw_free_recv_priv
  staging: vt6656: Removed unused variable vt3342_vnt_threshold
  staging: vt6656: Removed unused variable bb_vga_0
  staging: remove ashmem
  ...
 2022-03-28 12:50:50 -07:00
Linus Torvalds
02e2af20f4 Char/Misc and other driver updates for 5.18-rc1 
Here is the big set of char/misc and other small driver subsystem
 updates for 5.18-rc1.
 
 Included in here are merges from driver subsystems which contain:
 	- iio driver updates and new drivers
 	- fsi driver updates
 	- fpga driver updates
 	- habanalabs driver updates and support for new hardware
 	- soundwire driver updates and new drivers
 	- phy driver updates and new drivers
 	- coresight driver updates
 	- icc driver updates
 
 Individual changes include:
 	- mei driver updates
 	- interconnect driver updates
 	- new PECI driver subsystem added
 	- vmci driver updates
 	- lots of tiny misc/char driver updates
 
 There will be two merge conflicts with your tree, one in MAINTAINERS
 which is obvious to fix up, and one in drivers/phy/freescale/Kconfig
 which also should be easy to resolve.
 
 All of these have been in linux-next for a while with no reported
 problems.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc and other driver updates from Greg KH:
 "Here is the big set of char/misc and other small driver subsystem
  updates for 5.18-rc1.

  Included in here are merges from driver subsystems which contain:

   - iio driver updates and new drivers

   - fsi driver updates

   - fpga driver updates

   - habanalabs driver updates and support for new hardware

   - soundwire driver updates and new drivers

   - phy driver updates and new drivers

   - coresight driver updates

   - icc driver updates

  Individual changes include:

   - mei driver updates

   - interconnect driver updates

   - new PECI driver subsystem added

   - vmci driver updates

   - lots of tiny misc/char driver updates

  All of these have been in linux-next for a while with no reported
  problems"

* tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (556 commits)
  firmware: google: Properly state IOMEM dependency
  kgdbts: fix return value of __setup handler
  firmware: sysfb: fix platform-device leak in error path
  firmware: stratix10-svc: add missing callback parameter on RSU
  arm64: dts: qcom: add non-secure domain property to fastrpc nodes
  misc: fastrpc: Add dma handle implementation
  misc: fastrpc: Add fdlist implementation
  misc: fastrpc: Add helper function to get list and page
  misc: fastrpc: Add support to secure memory map
  dt-bindings: misc: add fastrpc domain vmid property
  misc: fastrpc: check before loading process to the DSP
  misc: fastrpc: add secure domain support
  dt-bindings: misc: add property to support non-secure DSP
  misc: fastrpc: Add support to get DSP capabilities
  misc: fastrpc: add support for FASTRPC_IOCTL_MEM_MAP/UNMAP
  misc: fastrpc: separate fastrpc device from channel context
  dt-bindings: nvmem: brcm,nvram: add basic NVMEM cells
  dt-bindings: nvmem: make "reg" property optional
  nvmem: brcm_nvram: parse NVRAM content into NVMEM cells
  nvmem: dt-bindings: Fix the error of dt-bindings check
  ...
 2022-03-28 12:27:35 -07:00
Ansuel Smith
887646c47d dt-bindings: reset: add ipq8064 ce5 resets 
Add ipq8064 ce5 resets needed for CryptoEngine gcc driver.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Tested-by: Jonathan McDowell <noodles@earth.li>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220226135235.10051-14-ansuelsmth@gmail.com
 2022-03-08 16:19:31 -06:00
Robert Marko
440c7317e4 dt-bindings: reset: Add Delta TN48M 
Add header for the Delta TN48M CPLD provided
resets.

Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Link: https://lore.kernel.org/r/20220131133049.77780-4-robert.marko@sartura.hr
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2022-02-25 09:59:35 +01:00
Vidya Sagar
d06a171e07 dt-bindings: Add Tegra234 PCIe clocks and resets 
Add the clocks and resets used by the PCIe hardware found on
Tegra234 SoCs.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2022-02-24 19:56:16 +01:00
Mohan Kumar
07d743902a dt-bindings: Add HDA support for Tegra234 
Add hda clocks, memory ,power and reset binding entries
for Tegra234.

Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2022-02-24 18:34:33 +01:00
Akhil R
38eb21a5fc dt-bindings: Add headers for Tegra234 PWM 
Add dt-bindings header files for PWM of Tegra234

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2022-02-03 18:43:17 +01:00
Akhil R
bb747becf8 dt-bindings: Add headers for Tegra234 I2C 
Add dt-bindings header files for I2C controllers for Tegra234

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2022-02-03 18:43:00 +01:00
Sergio Paracuellos
f383b07706 dt-bindings: reset: add dt binding header for Mediatek MT7621 resets 
Add dt binding header for resets lines in Mediatek MT7621 SoCs.

Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20220110114930.1406665-2-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2022-01-26 13:04:46 +01:00
Linus Torvalds
455e73a07f We have a couple patches in the framework core this time around but 
they're mostly minor cleanups and some debugfs stuff. The real work
 that's in here is the typical pile of clk driver updates and new SoC
 support. Per usual (or maybe just recent trends), Qualcomm gains a
 handful of SoC drivers additions and has the largest diffstat. After
 that there are quite a few updates to the Allwinner (sunxi) drivers to
 support modular drivers and Renesas is heavily updated to add more
 support for various clks. Overall it looks pretty normal.
 
 New Drivers:
  - Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770
  - MediaTek mt7986 SoC basic support
  - Clock and reset driver for Toshiba Visconti SoCs
  - Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8)
  - Allwinner D1 clks
  - Lan966x Generic Clock Controller driver and associated DT bindings
  - Qualcomm SDX65, SM8450, and MSM8976 GCC clks
  - Qualcomm SDX65 and SM8450 RPMh clks
 
 Updates:
  - Set suppress_bind_attrs to true for i.MX8ULP driver
  - Switch from do_div to div64_ul for throughout all i.MX drivers
  - Fix imx8mn_clko1_sels for i.MX8MN
  - Remove unused IPG_AUDIO_ROOT from i.MX8MP
  - Switch parent for audio_root_clk to audio ahb in i.MX8MP driver
  - Removal of all remaining uses of __clk_lookup() in drivers/clk/samsung
  - Refactoring of the CPU clocks registration to use common interface
  - An update of the Exynos850 driver (support for more clock domains)
    required by the E850-96 development board
  - Prep for runtime PM and generic power domains on Tegra
  - Support modular Allwinner clk drivers via platform bus
  - Lan966x clock driver extended to support clock gating
  - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
    thermal (TSU) clocks and resets on Renesas RZ/G2L
  - Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2 clock
    drivers, and in the Renesas SDHI driver
  - Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable
  - Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC
  - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
  - Add GPU clock and resets on Renesas RZ/G2L
  - Add clk-provider.h to various Qualcomm clk drivers
  - devm version of clk_hw_register_gate()
  - kerneldoc fixes in a couple drivers
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "We have a couple patches in the framework core this time around but
  they're mostly minor cleanups and some debugfs stuff. The real work
  that's in here is the typical pile of clk driver updates and new SoC
  support.

  Per usual (or maybe just recent trends), Qualcomm gains a handful of
  SoC drivers additions and has the largest diffstat. After that there
  are quite a few updates to the Allwinner (sunxi) drivers to support
  modular drivers and Renesas is heavily updated to add more support for
  various clks.

  Overall it looks pretty normal.

  New Drivers:
   - Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770
   - MediaTek mt7986 SoC basic support
   - Clock and reset driver for Toshiba Visconti SoCs
   - Initial clock driver for the Exynos7885 SoC (Samsung Galaxy A8)
   - Allwinner D1 clks
   - Lan966x Generic Clock Controller driver and associated DT bindings
   - Qualcomm SDX65, SM8450, and MSM8976 GCC clks
   - Qualcomm SDX65 and SM8450 RPMh clks

  Updates:
   - Set suppress_bind_attrs to true for i.MX8ULP driver
   - Switch from do_div to div64_ul for throughout all i.MX drivers
   - Fix imx8mn_clko1_sels for i.MX8MN
   - Remove unused IPG_AUDIO_ROOT from i.MX8MP
   - Switch parent for audio_root_clk to audio ahb in i.MX8MP driver
   - Removal of all remaining uses of __clk_lookup() in
     drivers/clk/samsung
   - Refactoring of the CPU clocks registration to use common interface
   - An update of the Exynos850 driver (support for more clock domains)
     required by the E850-96 development board
   - Prep for runtime PM and generic power domains on Tegra
   - Support modular Allwinner clk drivers via platform bus
   - Lan966x clock driver extended to support clock gating
   - Add serial (SCI1), watchdog (WDT), timer (OSTM), SPI (RSPI), and
     thermal (TSU) clocks and resets on Renesas RZ/G2L
   - Rework SDHI clock handling in the Renesas R-Car Gen3 and RZ/G2
     clock drivers, and in the Renesas SDHI driver
   - Make the Cortex-A55 (I) clock on Renesas RZ/G2L programmable
   - Document support for the new Renesas R-Car S4-8 (R8A779F0) SoC
   - Add support for the new Renesas R-Car S4-8 (R8A779F0) SoC
   - Add GPU clock and resets on Renesas RZ/G2L
   - Add clk-provider.h to various Qualcomm clk drivers
   - devm version of clk_hw_register_gate()
   - kerneldoc fixes in a couple drivers"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (131 commits)
  clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup()
  clk: mediatek: add mt7986 clock support
  clk: mediatek: add mt7986 clock IDs
  dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC
  clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers
  clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper
  clk: x86: Fix clk_gate_flags for RV_CLK_GATE
  clk: x86: Use dynamic con_id string during clk registration
  ACPI: APD: Add a fmw property clk-name
  drivers: acpi: acpi_apd: Remove unused device property "is-rv"
  x86: clk: clk-fch: Add support for newer family of AMD's SOC
  clk: ingenic: Add MDMA and BDMA clocks
  dt-bindings: clk/ingenic: Add MDMA and BDMA clocks
  clk: bm1880: remove kfrees on static allocations
  clk: Drop unused COMMON_CLK_STM32MP157_SCMI config
  clk: st: clkgen-mux: search reg within node or parent
  clk: st: clkgen-fsyn: search reg within node or parent
  clk: Enable/Disable runtime PM for clk_summary
  MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller
  clk: visconti: Add support common clock driver and reset driver
  ...
 2022-01-12 17:02:27 -08:00
Stephen Boyd
1d0bd126d9 Merge branches 'clk-socfpga', 'clk-toshiba', 'clk-st' and 'clk-bitmain' into clk-next 
- Clock and reset driver for Toshiba Visconti SoCs

* clk-socfpga:
  clk: socfpga: s10: Make use of the helper function devm_platform_ioremap_resource()
  clk: socfpga: agilex: Make use of the helper function devm_platform_ioremap_resource()
  clk: socfpga: remove redundant assignment after a mask operation
  clk: socfpga: remove redundant assignment on division

* clk-toshiba:
  clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup()
  MAINTAINERS: Add entries for Toshiba Visconti PLL and clock controller
  clk: visconti: Add support common clock driver and reset driver
  dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV770x SoC
  dt-bindings: clock: Add DT bindings for PLL of Toshiba Visconti TMPV770x SoC

* clk-st:
  clk: Drop unused COMMON_CLK_STM32MP157_SCMI config
  clk: st: clkgen-mux: search reg within node or parent
  clk: st: clkgen-fsyn: search reg within node or parent

* clk-bitmain:
  clk: bm1880: remove kfrees on static allocations
 2022-01-11 18:30:50 -08:00
Linus Torvalds
bb4ed26e7e SoC: Add support for StarFive JH7100 RISC-V SoC 
This adds support for the StarFive JH7100, including the necessary
 device drivers and DT files for the BeagleV Starlight prototype
 board, with additional boards to be added later. This SoC promises
 to be the first usable low-cost platform for RISC-V.
 
 I've taken this through the SoC tree in the anticipation of adding
 a few other Arm based SoCs as well, but those did not pass the
 review in time, so it's only this one.
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Merge tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull RISC-V SoC updates from Arnd Bergmann:
 "Add support for StarFive JH7100 RISC-V SoC

  This adds support for the StarFive JH7100, including the necessary
  device drivers and DT files for the BeagleV Starlight prototype board,
  with additional boards to be added later. This SoC promises to be the
  first usable low-cost platform for RISC-V.

  I've taken this through the SoC tree in the anticipation of adding a
  few other Arm based SoCs as well, but those did not pass the review in
  time, so it's only this one"

* tag 'newsoc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  reset: starfive-jh7100: Fix 32bit compilation
  RISC-V: Add BeagleV Starlight Beta device tree
  RISC-V: Add initial StarFive JH7100 device tree
  serial: 8250_dw: Add StarFive JH7100 quirk
  dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts
  pinctrl: starfive: Add pinctrl driver for StarFive SoCs
  dt-bindings: pinctrl: Add StarFive JH7100 bindings
  dt-bindings: pinctrl: Add StarFive pinctrl definitions
  reset: starfive-jh7100: Add StarFive JH7100 reset driver
  dt-bindings: reset: Add Starfive JH7100 reset bindings
  dt-bindings: reset: Add StarFive JH7100 reset definitions
  clk: starfive: Add JH7100 clock generator driver
  dt-bindings: clock: starfive: Add JH7100 bindings
  dt-bindings: clock: starfive: Add JH7100 clock definitions
  dt-bindings: interrupt-controller: Add StarFive JH7100 plic
  dt-bindings: timer: Add StarFive JH7100 clint
  RISC-V: Add StarFive SoC Kconfig option
 2022-01-10 08:32:37 -08:00
Nobuhiro Iwamatsu
ffa81a0326 dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV770x SoC 
Add device tree bindings for SMU (System Management Unit) controller of
Toshiba Visconti TMPV770x SoC series.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20211025031038.4180686-3-nobuhiro1.iwamatsu@toshiba.co.jp
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2022-01-05 17:05:21 -08:00
Geert Uytterhoeven
810e287e83 dt-bindings: reset: Add StarFive JH7100 reset definitions 
Add all resets for the StarFive JH7100 reset controller.

Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
to all definitions.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
 2021-12-16 17:24:23 +01:00
Mikko Perttunen
fc5e0e3762 dt-bindings: Update headers for Tegra234 
Add a few more clocks that will be used in follow-up patches to enable
more functionality on Tegra234.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2021-12-16 16:43:49 +01:00
Samuel Holland
c962f10f39
dt-bindings: clk: Add compatibles for D1 CCUs 
The D1 has a CCU and a R_CCU (PRCM CCU) like most other sunxi SoCs, with
3 and 4 clock inputs, respectively. Add the compatibles and bindings.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211119043545.4010-2-samuel@sholland.org
 2021-11-23 10:29:05 +01:00