The code that waits for the pipeline empty condition of the MSU is
currently called in the path that disables the trace. We will also
need this in the window switch trigger sequence. Therefore, factor
out this code and make it accessible to the GTH device.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Instead of using a home-grown array of pointers to the DMA pages, switch
over to scatterlist data types and accessors, which has all the convenient
accessors, can be used to batch-map DMA memory and is convenient for
passing around between different layers, which will be useful when MSU
buffer management has to cross the boundaries of the MSU driver.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
There are a few places in the code where open-coded versions of list entry
accessors list_first_entry()/list_last_entry()/list_next_entry() are used.
Replace those with the standard macros.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
The only type of IRQ triggering event that is useful to us at the moment
is the "last block" interrupt of the MSU. This interrupt can only be
enabled via "MINTCTL" register that doesn't exist in earlier version of
the Intel TH.
Enumerate the presence of MINTCTL via per-device driver data structure
and only instantiate the IRQ resource for subdevices if this capability
is present.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
We intend to use the interrupt to detect Last Block condition in the MSU
driver, which we can use for double-buffering software-managed data
transfers.
Add an interrupt handler to the MSU driver.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Since Intel TH is capable of MSI interrupt signalling, make use of it.
The way it works is, each of the 7 interrupt triggering events has its
own vector in this mode, as opposed to interrupt line delivery, where
all events are signalled via the same line. Failing to enable MSI, the
driver falls back to using an interrupt line.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Currently, the IRQ is passed between the glue layers and the core as a
separate argument, while the MMIO resources are passed as resources.
This also limits the number of IRQs thus used to one, while the current
versions of Intel TH use a different MSI vector for each interrupt
triggering event, of which there are 7.
Change this to pass IRQ in the resources array.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
In some versions of Intel TH, the Software Trace Hub (STH) has a second
MMIO BAR dedicated to the input from Intel PT. This calls for a new
subdevice that will be enumerated if the corresponding BAR is present.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
If a subdevice requires an MMIO region that wasn't in the resources passed
down from the glue layer, don't instantiate it, but don't error out. This
means that that particular subdevice doesn't exist for this instance of
Intel TH, which is a perfectly normal situation. This applies, for example,
to the "rtit" source device.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Currently, MMIO resource numbers in the TH driver core correspond to
PCI BAR numbers, because in the beginning there was only the PCI glue
layer. This created some confusion when the ACPI glue layer was added.
To avoid confusion and remove glue-specific code from the driver core,
split the resource indices between core and glue layers and change the
API so that the driver core receives the MMIO resources in the same
fixed order. At the same time, make the IRQ always be a parameter to
intel_th_alloc() instead of sometimes passing it as a resource.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Currently, the pages that are allocated for the single mode of MSC are not
mapped into the device's dma space and the code is incorrectly using
*_to_phys() in place of a dma address. This fails with IOMMU enabled and
is otherwise bad practice.
Fix the single mode buffer allocation to map the pages into the device's
DMA space.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Fixes: ba82664c13 ("intel_th: Add Memory Storage Unit driver")
Cc: stable@vger.kernel.org # v4.4+
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Here are the GNSS updates for 5.2-rc1; only a new u-blox compatible.
All have been in linux-next with no reported issues.
Signed-off-by: Johan Hovold <johan@kernel.org>
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Merge tag 'gnss-5.2-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss into char-misc-next
Johan writes:
GNSS updates for 5.2-rc1
Here are the GNSS updates for 5.2-rc1; only a new u-blox compatible.
All have been in linux-next with no reported issues.
Signed-off-by: Johan Hovold <johan@kernel.org>
* tag 'gnss-5.2-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss:
gnss: ubx: add u-blox,neo-6m compatible
dt-bindings: gnss: add u-blox,neo-6m compatible
Oded writes:
This tag contains further changes for kernel 5.2.
The changes are either bug fixes or simple re-factoring of existing code.
The notable changes are:
- Add missing fields in the bmon structure that is passed in the debug
IOCTL when the user wants to configure the bus monitor.
- Use the dedicated device-CPU accessible memory pool for all host memory
allocations that are accessible directly by the embedded CPU. This is
needed to enforce certain restrictions we have due to the embedded CPU's
architecture.
- Manipulate DMA addresses only inside ASIC-specific files. This is needed
to better support future ASICs code.
Other minor changes include:
- Move pr_fmt() to c files to avoid dependency in include order.
- Remove call to CS parsing function for workloads that originates from
the driver and remove dead code as a result from this change.
- Update names of structure members and labels to better reflect their
usage.
- When moving the dram PCI bar aperture, return the old aperture address
range instead of error code. This will allow us to restore the old
address range in a simpler fashion.
* tag 'misc-habanalabs-next-2019-05-03' of git://people.freedesktop.org/~gabbayo/linux:
habanalabs: Update CPU DMA memory label name
habanalabs: Update CPU DMA pool label name
habanalabs: increase timeout if working with simulator
habanalabs: remove condition that is always true
habanalabs: remove redundant member from parser struct
habanalabs: Manipulate DMA addresses in ASIC functions
habanalabs: rename functions to improve code readability
habanalabs: remove call to cs_parser()
habanalabs: Use single pool for CPU accessible host memory
habanalabs: return old dram bar address upon change
habanalabs: rename restore to ctx_switch when appropriate
habanalabs: use ASIC functions interface for rreg/wreg
uapi/habanalabs: add missing fields in bmon params
habanalabs: re-factor goya_parse_cb_no_ext_queue()
habanalabs: Cancel pr_fmt() definition dependency on includes order
Since CoreSight hardware topology can use a 'hidden' funnel in the
trace data path, this kind funnel doesn't have register for accessing
and is used by default from hardware design perspective. Below is an
example for related hardware topology:
+------+ +------+
| cpu0 |->| ETM |-\
+------+ +------+ \-> +--------+ +-----+
...... | Funnel |->| ETF |-\ Hidden funnel
+------+ +------+ /-> +--------+ +-----+ \ |
| cpu3 |->| ETM |-/ \ V
+------+ +------+ \-> +--------+
| Funnel |-> ...
+------+ +------+ /-> +--------+
| cpu4 |->| ETM |-\ /
+------+ +------+ \-> +--------+ +-----+ /
...... | Funnel |->| ETF |-/
+------+ +------+ /-> +--------+ +-----+
| cpu7 |->| ETM |-/
+------+ +------+
The CoreSight funnel driver only supports dynamic funnel with
registration register resource, thus it cannot support for the static
funnel case and it's impossible to create trace data path for this case.
This patch is to extend CoreSight funnel driver to support both for
static funnel and dynamic funnel. For the dynamic funnel it reuses the
code existed in the driver, for static funnel the driver will support
device probe if without providing register resource and the driver skips
registers accessing when detect the register base is NULL.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Wanglai Shi <shiwanglai@hisilicon.com>
Suggested-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Following the same fashion with replicator DT binding, this patch is to
unify the DT binding for funnel to support static and dynamic modes;
finally we get the funnel DT binding as below:
Before patch:
Static funnel, aka. non-configurable funnel:
Not supported;
Dynamic funnel, aka. configurable funnel:
"arm,coresight-funnel", "arm,primecell";
After patch:
Static funnel:
"arm,coresight-static-funnel";
Dynamic funnel:
"arm,coresight-dynamic-funnel", "arm,primecell";
"arm,coresight-funnel", "arm,primecell"; (obsolete)
At the end of this patch, it gives an example for static funnel DT
binding, and updates the dynamic funnel example.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Wanglai Shi <shiwanglai@hisilicon.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch adds a device id for the new static replicator compatible
string; it changes the driver name from "coresight-replicator" to
"coresight-static-replicator" as well.
This patch also gives warning when use the replicator obsolete DT
binding.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CoreSight uses below bindings for replicator:
Dynamic replicator, aka. configurable replicator:
"arm,coresight-dynamic-replicator", "arm,primecell";
Static replicator, aka. non-configurable replicator:
"arm,coresight-replicator";
The compatible string "arm,coresight-replicator" is not an explicit
naming to express the replicator is 'static'. To unify the naming
convention, this patch introduces a new compatible string
"arm,coresight-static-replicator" for the static replicator; the
compatible string "arm,coresight-replicator" is kept for backward
compatibility, but tag it as obsolete and suggest to use the new
compatible string.
As result CoreSight replicator have below bindings:
Dynamic replicator:
"arm,coresight-dynamic-replicator", "arm,primecell";
Static replicator:
"arm,coresight-static-replicator";
"arm,coresight-replicator"; (obsolete)
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Multi-blank lines do not help readability so remove them
Checkpatch complains:
CHECK: Please don't use multiple blank lines
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
For improving code readability it helps to have a blank line between
function so add when missing.
Checkpatch complains:
CHECK: Please use a blank line after function/struct/union/enum
declarations
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
macro argument should be inside a parenthesis to avoid precedence
issues
checkpatch complains:
CHECK: Macro argument 'n' may be better as '(n)' to avoid
precedence issues
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Found few more typos in the code, fix them
CHECK: 'and and' may be misspelled - perhaps 'and'?
CHECK: 'smaple' may be misspelled - perhaps 'sample'?
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Modify the code to avoid multiple assignments by assigning to variable
after error checks in soundwire bus.
CHECK: multiple assignments should be avoided
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Found few more issues reported checkpatch on code alignment so fix those
as well in the intel module.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Found few more issues reported checkpatch on code alignment so fix those
as well in the soundwire core.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Checkpatch warns that function definition of __sdw_register_driver
misses argument, so add it
WARNING: function definition argument 'struct module *' should also have
an identifier name
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux code style doesn't expect empty lines after braces and
gives warning:
CHECK: Blank lines aren't necessary after an open brace '{'
Remove the empty line in intel module
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux code style doesn't expect empty lines after braces and
gives warning:
CHECK: Blank lines aren't necessary after an open brace '{'
Remove the empty line in cadence lib
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Linux code style doesn't expect empty lines before or after braces and
gives warning:
CHECK: Blank lines aren't necessary after an open brace '{'
CHECK: Blank lines aren't necessary before a close brace '}'
Fix these instances in soundwire core
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Some more headers had C++ style SDPX line, fix that and change copyright
so that it is consistent with rest of the code in subsystem
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Move to help format instead of --help-- as that is not recommended and
this makes file consistent with other instance
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
For some reason the newlines are not used everywhere. Fix as needed.
Reported-by: Joe Perches <joe@perches.com>
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
No need for explicit test against true
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
No need for explicit test against true
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
No need for explicit test against true
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Use Linux style. In some cases parenthesis alignment is modified to
keep the code readable.
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
tools complain here and the location of the newline does not improve
readability.
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
no need for an explicit test against false
reported by Coccinelle
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
and make the code more readable
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
