ExynosAutov9 gained a reboot-mode node, so document the property to fix
warning:
exynosautov9-sadk.dtb: system-controller@10460000: 'reboot-mode' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220706160257.27579-3-krzysztof.kozlowski@linaro.org
Preferred coding for referencing other schemas is to use absolute path.
Quotes over path are also not needed.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220706160257.27579-2-krzysztof.kozlowski@linaro.org
Compatibles can come in two formats. Either "vendor,ip-soc" or
"vendor,soc-ip". Add a DT schema documenting preferred policy and
enforcing it for all new compatibles, except few existing patterns. The
schema also disallows wild-cards used in SoC compatibles.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220705161340.493474-1-krzysztof.kozlowski@linaro.org
Just a small bunch of miscellaneous updates: addition of missing
cache-level property to L2 caches on Juno, whitespace adjustments
and removal of erroneous 'mbox-name' and 'panel-dpi' compatible in
the device tree nodes.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEunHlEgbzHrJD3ZPhAEG6vDF+4pgFAmLFVroACgkQAEG6vDF+
4phMGA/+LPM48FsZSAOyOQdt0fFPLEPcXBn92aRVkDDie2RN5EnlEbBG0fmQZwzJ
dIEYlzs4KLxq8Ucj6ThdoVoW/POqPyyZjgzqGf32ltL6xs2KE/OO3Rtb1VSEOnQE
s3UvbGZ9qHv0XXx4yRr+06jJZ7Ll7nhKG4HtRL+vs3sGe67aWa05hX/F+l+20XEg
/PGhACF5W9do2e901JuUfAAw7vjTtyQFiC/JWGOzlzHqdC2x8+B5cyVvqeyfjdOj
vkfo0KaGiLBveszhwENupdpqVY5MmEVGcMyPRFBujSKBTakLvk/RE4eFb7GDd14F
f7xdZlgwjLYA5ihmbqwvtLif1F5a/zwvaH8yASN3K1sFMRdP90bOf1Bp9rKpqnBW
GW/F40y7QhfraF+3FSSloJj9pGUSkndKjz2yJKeGmMbU036Vjps9M8Zof6IyyEA2
uVRuh2anaBQLipOaY86z+8MXtZ+Hmxt11jDPf6HhKAGjIkvqB8OQtrTB+u9pmMyl
FDXehCVPng90P2d/8RYMvqq4yvHnGCdl3y9M1bhANH7yHqTsgFQSUkepZrKTY+hr
xTKFeEaAjsMlfOi/6dChXtMGUElgGdUgFRxB2WQKZfetgz2rBGqImJsV/nJl+Fd7
m3/Hxx5dkDvvUApXhffomWiFdoYFmDm1PIZqHhZHEP8KfBNNnPQ=
=ZJmi
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLFeBYACgkQmmx57+YA
GNl55Q//eRNl4TfNOZHFfnHK4yEfVmiJ3mAqwoeHQog2YelAiT1hCDb9J4dvVwTT
V4/JtUFUQuHFJVO0zFGob71XnxhgQzYTyJHbOhAxSHMrjNk20Fy+tJIv0D4AmG+S
G15KPEbdSfECg1QkZCDAsPFXJeKzNmGklvtu9mBtod31A2eIaj7GQsFIsOFKfF+y
MQUvo+DjE4SOxCZdjAxvSY3hV2fYgzFS5OIzmpI25KDlr/NnGS+6kJKWVEnc+HVT
beAAqNbJUeH9Y4dmzYXMCmSQlS/L1peNZxXpJODZxw8zYLEmbDzHYONKLQ+38ASA
FHAsbpgdrFPHZFAMDnLhaeBXAxGg3QhMG0ka5aGz3ro0j0nkhQUbf1hdP4roiZIN
7K6B1z8QmyPYGMo5EWsjiM/J4ePRllQrhENW1OKrXADJovVKya2bnNUOZI8VBB8g
LKGr6lh0V2mdcoD7jJb33PB2x//10P6Ge+XlJWNxui360p8VzTtweUq4/7Z7tjzJ
B3YOFCHB3qza0sqBSUGIE8SHhx4vf2RR31jx3Tael9xfjBpfYGRRQMLbKZEUfFoH
bYH2IDyItvrdFazDsEcXcmWnelgY9kelIjv915cPY+Fr/XduVSHcJJ+E+JDGTcuN
pGuj6eBR7kzRQjVXfySNxsdQ5TSNq0uw5xBcNM3flrip0AxrWJc=
=OxuR
-----END PGP SIGNATURE-----
Merge tag 'juno-updates-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt
Armv8 Juno/FVP updates for v5.20
Just a small bunch of miscellaneous updates: addition of missing
cache-level property to L2 caches on Juno, whitespace adjustments
and removal of erroneous 'mbox-name' and 'panel-dpi' compatible in
the device tree nodes.
* tag 'juno-updates-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: juno: Add cache-level property to L2 caches
arm64: dts: arm: adjust whitespace around '='
arm64: dts: arm/juno: Drop erroneous 'mbox-name' property
arm64: dts: arm/fvp-base-revc: Remove 'panel-dpi' compatible
Link: https://lore.kernel.org/r/20220706115026.2272643-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
It contains:
- compilation warning fixes for SAMA5D2
- updates for all AT91 device tree to use generic name for reset
controller
- reset controller node for SAMA7G5
- MCAN1 and UDPHS nodes for LAN966 SoCs
- Flexcom3 bindings were updated for lan966x-pcb8291.dts board to cope
with reality
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCYsPyogAKCRCejrg/N2X7
/Uq7AQCAKfITIfmP9EY0JGuhJqBNNGckbCEkFLbixz6uj5TFNAEAxoJmmcL5cj9m
wUczRNYOD8wW7R1GoLOsHF95pwJvhgI=
=rxjU
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLFdTYACgkQmmx57+YA
GNk3Dw/9EQXALu+c9PNgJ5nNwBH0NifSYVAS6K/nPbbVUGfp8kJaPBkHfFWjJzPd
F+cEK31mp28kwA9GQTlAkkWIomrBDRsl+Xe4Dmwtbno4AkfsvsTskFWAdmgDMHGb
GAasQGXPfr6e+KvTARcUYvA4ff4GkZG+d3o8sCEs001PGVTHHBLC5Od0ezBxA3OO
JWG1Giruy/u8v+9zjmEmgJEAp7XIt+f2kPI4qCxT/okLAmX5fk+IL/eybys1ASXi
g4qFHXwT/pH5DrBmFlBpCz4gYZ2PKqfSOz25xvP167Crtv7HUrvmfoI+SEzzlzbr
mfHSVTbGfgJ23aFhW5pSAm8X8P1gMMfPgRSJaX/QUb61+tWnX+E13H6WsvwL5hBw
Ybbn2KB1qSXWXbtAFehMcTxmUnXMD8rzZ1pHGRl8JeJJ0Al4sxutPVSLgKivQ4RT
6SHBG5jlQ+VEw15AsvmRgdnDuLcqU/7pHh3BOWArnwsymsq00kmwBEsyahoWZZoV
REneCjaX9kwzKGdS7jYZFUp8001VKjR7IYuGrsX4sal0+5c56Keg0YfZLc0U+Ss4
NTLTbb5rzx2M0zyxqmc9vqOagwYacdgMrCbgRVIW1uB4UfCjO4G/94FIZjXgQ9rz
hv2GX0iHgYKpAPgOcvV8NoRa/t4zMAXNuer+5oMiW27H2E4NzXY=
=182f
-----END PGP SIGNATURE-----
Merge tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt
AT91 DT for v5.20
It contains:
- compilation warning fixes for SAMA5D2
- updates for all AT91 device tree to use generic name for reset
controller
- reset controller node for SAMA7G5
- MCAN1 and UDPHS nodes for LAN966 SoCs
- Flexcom3 bindings were updated for lan966x-pcb8291.dts board to cope
with reality
* tag 'at91-dt-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: lan966x: Add UDPHS support
dt-bindings: usb: atmel: Add Microchip LAN9662 compatible string
ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings.
ARM: dts: lan966x: Add mcan1 node.
ARM: dts: at91: sama7g5: add reset-controller node
ARM: dts: at91: use generic name for reset controller
ARM: dts: at91: sama5d2: fix compilation warning
ARM: dts: at91: sama5d2: fix compilation warning
Link: https://lore.kernel.org/r/20220705084637.818216-1-claudiu.beznea@microchip.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
on rk356x in general plus necessary board-specific changes on Rock-3A,
Quartz64-A, rk3568-evb, BPI-R2-Pro.
A number of additional peripherals on BPI-R2-Pro (gpu, thermal, rtc) and
PCIe2x1 support on rk3568 and enablement on Quart64-A as well as a number
of additional peripherals to this board (sfc node, sdr-104 support, fan).
And finally touch panel support for rockpro64 and some misc dt cleanups
(node names for dtschema and styling).
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAmLEGlUQHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgcG+CACtfU9yrfAxElsWY2cxkPJm3nV+rA6jO3VX
HLPFjyQ6XJlpHGQrKge38HPCaq/8tynxgt4mykdE3mUn7I8OCTylzW5OUtue4yJU
D35JHQbuhk79MlfgkD7Wp2iz9jwB64JgeCLzbVfUq5f7CiBqc9R1StWZwYqdlJ87
PS3dAGfO6hswJmbF2f4u2bc0OzPfQs0KkreiN2YkfmzffMo28VDGmumj2IPEPGEI
h7eHLrJT721YTaXXkErd0j9Fen6lngQybGoLGThBYxzLrfshRulW1uR6Ykx1PQBA
rz3nq9YhHaWz0uVn6EIN95c76LLkgU/WE5dypjduT12i21wQ/42y
=shlA
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLFc/4ACgkQmmx57+YA
GNktbQ//XNZFy22cJ6KiTJfjTudj5q1DfqJDZZPP8rwiV4rGUZu5GoxEp4gAfvky
Ds69aqemEOW4SU3XX8tNPp+6CulnZImSgXDiIHzMC8MMakR3Kj8si6NttA10/USO
EOUx/LJU7HxEsOQL2lmGi55eyoYZz7rOgzqa1W2rMOdzX/ytmvk124u6J5TDX2/8
w0i66LCTvlf+4P/+QK7riwOuzYxsWNaJgSg/+bVtfZwCXfddmDdYvh/JsrQKR7O8
uHDiE1FSBnn3Lyt1anNH8Lmya69vYmZpEkcMVMGAQPZ7WDIPPTVgH4mzOLmrLges
WbQtDWe3K5AETZ5hQDdnBkVfiGtPd0Nnb+jbU0VYWNRDupiptoHwYbORupOAmd6Z
iciexDxREu7Z4qBmOVFKsgKpLKJZUFT7hXxvU8Mqpwx9XLufT347ehUj/mLxMMpn
HnAB+URzdI7RP2m9g0bMDQZIR48BAyu/pS2r+Q2hw/NJTrC3Y9RIb2xqjNp4+r4N
SYdSbGs0iZXZzEbor/INWd3ImdqDV/B5SXEhE0GmJBaXy2s3BN8/jMboewr5+Mxt
oSM+Lbidcb2FhOpAB2eTVbLoJ+bkyzqY8WYlBNj6QjEll2pDz+ff3uuIZ3Ka7aBB
0Org6/qdQ7kphklAz93td0zjTOtiF5bgQswpe78evpdZie5dyw8=
=owCF
-----END PGP SIGNATURE-----
Merge tag 'v5.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt
New board the Radxa Rock Pi S, enablement of graphics support and hdmi-audio
on rk356x in general plus necessary board-specific changes on Rock-3A,
Quartz64-A, rk3568-evb, BPI-R2-Pro.
A number of additional peripherals on BPI-R2-Pro (gpu, thermal, rtc) and
PCIe2x1 support on rk3568 and enablement on Quart64-A as well as a number
of additional peripherals to this board (sfc node, sdr-104 support, fan).
And finally touch panel support for rockpro64 and some misc dt cleanups
(node names for dtschema and styling).
* tag 'v5.20-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (27 commits)
arm64: dts: rockchip: enable hdmi tx audio on rock-3a
arm64: dts: rockchip: enable hdmi tx audio on rk3568-evb1-v10
arm64: dts: rockchip: align gpio-key node names with dtschema
arm64: dts: rockchip: rock-pi-s add more peripherals
arm64: dts: rockchip: add ROCK Pi S DTS support
dt-bindings: arm: rockchip: Add Radxa ROCK Pi S
arm64: dts: rockchip: Add missing space around regulator-name on rk3368-orion-r68
arm64: dts: rockchip: enable the gpu on BPI-R2-Pro
arm64: dts: rockchip: configure thermal shutdown for BPI-R2-Pro
arm64: dts: rockchip: Enable HDMI audio on BPI R2 Pro
arm64: dts: rockchip: enable vop2 and hdmi tx on BPI-R2-Pro
arm64: dts: rockchip: set display regulators to always-on on BPI-R2-Pro
arm64: dts: rockchip: add RTC to BPI-R2 Pro
arm64: dts: rockchip: Enable HDMI audio on Quartz64 A
arm64: dts: rockchip: Add HDMI audio nodes to rk356x
arm64: dts: rockchip: adjust whitespace around '='
arm64: dts: rockchip: enable vop2 and hdmi tx on rock-3a
arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a
arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi
arm64: dts: rockchip: rk356x: Add HDMI nodes
...
Link: https://lore.kernel.org/r/40088956.J2Yia2DhmK@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Universal Serial Interface (USI) supports three types of serial interface
such as Universal Asynchronous Receiver and Transmitter (UART), Serial
Peripheral Interface (SPI), and Inter-Integrated Circuit (I2C).
Each protocols can be working independently and configured as one of
those using external configuration inputs.
Exynos Auto v9 SoC support 12 USIs. When a USI uses two pins such as i2c
and 3 wire uarts(RX/TX only), we can use remain two pins as i2c mode.
So, we can define one USI node that includes serial/spi and hsi2c.
usi_i2c nodes can be used only for i2c mode.
We can have below combinations for one USI.
1) The usi node is used either 4 pin uart or 4 pin spi
-> No usi_i2c can be used
2) The usi node is used 2 pin uart(RX/TX) and i2c(SDA/SCL)
-> usi_i2c should be enabled to use the latter i2c
3) The usi node is used i2c(SDA/SCL) and i2c(SDA/SCL)
-> usi_i2c should be enabled to use the latter i2c
By default, all USIs are initially set to uart mode by below setting.
samsung,mode = <USI_V2_UART>;
You can change it either USI_V2_SPI or USI_V2_I2C.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220701015226.32781-6-chanho61.park@samsung.com
Before adding whole USI nodes, this applies the changes of usi0 in
advance. To be the usi0 and serian_0 nodes as SoC default, some
properties should be moved to exynosautov9-sadk.dts.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220701015226.32781-5-chanho61.park@samsung.com
Add samsung,exynosautov9-usi dedicated compatible for representing USI
of Exynos Auto v9 SoC.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220701015226.32781-2-chanho61.park@samsung.com
Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT.
Both the ST MIPID02 and DCMI are disabled by default, as the
AV96 camera module is optional.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for RCC pin, this is used on AV96 board
for e.g. sensor clock supply.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for DCMI pins, this is used on AV96 board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add DT for DH DRC Compact unit, which is a universal controller device.
The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD
card slot, eMMC and SDIO Wi-Fi.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for UART5 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for UART4 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for UART3 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for SPI2 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add another mux option for CAN1 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add DT compatible string for DH electronics STM32MP15xx DHCOR on DRC Compact
carrier board into YAML DT binding document. This system is a general purpose
DIN Rail Controller design.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Those pin comments refer to SPI2 pins, not SPI1 pins, update the comments.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add UDPHS (the USB High Speed Device Port controller) support.
The both lan966x SOCs (LAN9662 and LAN9668) have the same UDPHS
IP. This IP is also the same as the one present in the SAMA5D3
SOC.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704102845.168438-4-herve.codina@bootlin.com
The USB device controller available in the Microchip LAN9662 SOC
is the same IP as the one present in the SAMA5D3 SOC.
Add the LAN9662 compatible string and set the SAMA5D3 compatible
string as a fallback for the LAN9662.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704102845.168438-3-herve.codina@bootlin.com
Enables Reset and Clocks Controller on STM32MP13
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Like for stm32mp15, when stm32 RCC node is used to interact with a secure
context (using clock SCMI protocol), a different path has to be used for
yaml verification.
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: Rob Herring <robh@kernel.org>
According to the OSD32MP1 Power System overview[1] the EEPROM is connected to
the VDD line and not to some single-purpose fixed regulator.
Set the EEPROM supply according to the diagram to eliminate this parent-less
regulator.
[1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
According to the OSD32MP1 Power System overview[1] ldo3's input is always
internally connected to vdd_ddr.
[1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections
Signed-off-by: Leonard Göhrs <l.goehrs@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3
in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant
which has extra Empirion DCDC converter in front of the 1V8 IO supply, or
outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter.
The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily
high input voltage to the Empirion DCDC converter, so move it into matching
DTSI to stop confusing users.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The stm32 ipcc mailbox driver supports only two interrupts (rx and tx), so
remove the unsupported "wakeup" one.
Note that the EXTI interrupt 61 has two roles : it is hierarchically linked
to the GIC IPCC "rx" interrupt, and it acts as a wakeup source.
Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
The USBH composed of EHCI and OHCI controllers needs the PHY clock to be
initialized first, before enabling (gating) them. The reverse is also
required when going to suspend.
So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL
gets enabled 1st upon controller init. Upon suspend/resume, this also makes
the clock to be disabled/re-enabled in the correct order.
This fixes some IRQ storm conditions seen when going to low-power, due to
PHY PLL being disabled before all clocks are cleanly gated.
Fixes: 949a0c0dec ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c")
Fixes: db7be2cb87 ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
