- Remove allwinner workaround logic/compatible in fixed factor code
- MediaTek clk driver cleanups
- Add reset support to more MediaTek clk drivers
- devm helpers for clk_get() + clk_prepare() and clk_enable()
* clk-basic:
clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw()
clk: mux: Introduce devm_clk_hw_register_mux_parent_hws()
clk: divider: Introduce devm_clk_hw_register_divider_parent_hw()
dt-bindings: clock: fixed-factor: Drop Allwinner A10 compatible
clk: fixed: Remove Allwinner A10 special-case logic
* clk-mtk:
clk: mediatek: reset: Add infra_ao reset support for MT8186
dt-bindings: arm: mediatek: Add #reset-cells property for MT8186
dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186
clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195
dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195
clk: mediatek: reset: Add reset support for simple probe
clk: mediatek: reset: Add new register reset function with device
clk: mediatek: reset: Change return type for clock reset register function
clk: mediatek: reset: Support inuput argument index mode
clk: mediatek: reset: Support nonsequence base offsets of reset registers
clk: mediatek: reset: Revise structure to control reset register
clk: mediatek: reset: Merge and revise reset register function
clk: mediatek: reset: Extract common drivers to update function
clk: mediatek: reset: Refine and reorder functions in reset.c
clk: mediatek: reset: Fix written reset bit offset
clk: mediatek: reset: Add reset.h
clk: mediatek: Delete MT8192 msdc gate
dt-bindings: ARM: Mediatek: Remove msdc binding of MT8192 clock
* clk-devm-enable:
clk: Remove never used devm_clk_*unregister()
clk: Fix pointer casting to prevent oops in devm_clk_release()
clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()
clk: Provide new devm_clk helpers for prepared and enabled clocks
clk: generalize devm_clk_get() a bit
clk: Improve documentation for devm_clk_get() and its optional variant
* clk-ti-dt:
clk: ti: Stop using legacy clkctrl names for omap4 and 5
Add the devres and non-devres variant of
clk_hw_register_fixed_factor_parent_hw() for registering a fixed factor
clock with clk_hw parent pointer instead of parent name.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20220629225331.357308-4-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the devres variant of clk_hw_register_mux_hws() for registering a
mux clock with clk_hw parent pointers instead of parent names.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220629225331.357308-3-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add the devres variant of clk_hw_register_divider_parent_hw() for
registering a divider clock with clk_hw parent pointer instead of parent
name.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220629225331.357308-2-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
For the entire history of the devm_clk_*unregister() existence they were
used only once (*) in 2015. Remove them.
*) The commit 264e3b75de ("clk: s2mps11: Simplify s2mps11_clk_probe unwind
paths") exactly supports the point of the change proposed here.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220622171147.85603-1-andriy.shevchenko@linux.intel.com
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add an API for a fixed factor clk that uses an index for the parent
instead of a string name. This allows us to move drivers away from the
string based method of describing parents and use the DT/firmware based
method instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20220226040723.143705-2-marex@denx.de
[sboyd@kernel.org: Expose a new API instead of internal function]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The elements of the table are never modified in clk-mux.c. To make this
clear to clock drivers, declare the parameter as const u32 *table.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220205103613.1216218-4-j.neuschaefer@gmx.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add devm_clk_hw_register_gate() - devres-managed version of
clk_hw_register_gate()
Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchip.com
- Add power of two flag to fractional divider clk type
* clk-frac-divider:
clk: fractional-divider: Document the arithmetics used behind the code
clk: fractional-divider: Introduce POWER_OF_TWO_PS flag
clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience
clk: fractional-divider: Export approximation algorithm to the CCF users
The newly introduced POWER_OF_TWO_PS flag, when set, makes the flow
to skip the assumption that the caller will use an additional 2^scale
prescaler to get the desired clock rate.
Reported-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20210812170025.67074-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The providers are all located in drivers/clk/ and hence no need
to export the clock operations to wider audience. Hide them by
moving to drivers/clk/clk-fractional-divider.h.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20210812170025.67074-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The definition of CLK_MULTIPLIER_ROUND_CLOSEST is not aligned to the two
bit definitions next to it. A deeper inspection reveals that the
alignment of CLK_MULTIPLIER_ROUND_CLOSEST does match the most common
alignment.
Align the bit definitions for the various provider types throughout the
file at 40 columns, to increase uniformity.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5468cd9e50cda8fc59cb6baab9413c6c0de1a974.1626257689.git.geert+renesas@glider.be
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
These are useful when running on 32-bit systems to increase the upper
supported frequency limit. clk_ops.round_rate returns a signed long
which limits the maximum rate on 32-bit systems to 2^31 (or approx.
2.14GHz). clk_ops.determine_rate internally uses an unsigned long so
the maximum rate on 32-bit systems is 2^32 or approx. 4.29GHz.
To avoid code-duplication switch over divider_{ro_,}round_rate_parent
to use the new divider_{ro_,}determine_rate functions.
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210627223959.188139-2-martin.blumenstingl@googlemail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add devm_clk_hw_register_divider() - devres version of
clk_hw_register_divider().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210331105735.3690009-3-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Add devm_clk_hw_register_mux() - devres-managed version of
clk_hw_register_mux().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210331105735.3690009-2-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Add a devm helper for clk_hw_register_fixed_factor() so that drivers that internally
register fixed factor clocks for things like dividers don't need to manually unregister
them on remove or if probe fails.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210211052206.2955988-4-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk_register() is deprecated. Using 'clk' member of struct clk_hw is
discouraged. With this constraint, it is difficult for driver to
register clocks using the clk_hw API and then use the clock with
the consumer API
This adds a simple helper, clk_hw_get_clk(), to get a struct clk from
a struct clk_hw. Like other clk_get() variant, each call to this helper
must be balanced with a call to clk_put(). To make life easier on the
consumers, a memory managed version is provided as well.
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201021162147.563655-3-jbrunet@baylibre.com
Tested-by: Kevin Hilman <khilman@baylibre.com>
[sboyd@kernel.org: Fix kernel-doc]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
- Add support for SAMA7G5 SoC clks
- Microchip Sparx5 DPLL clk
* clk-microchip:
clk: sparx5: Add Sparx5 SoC DPLL clock driver
dt-bindings: clock: sparx5: Add bindings include file
* clk-mmp:
clk: mmp: avoid missing prototype warning
* clk-unused:
clk: drop unused function __clk_get_flags
* clk-at91:
clk: at91: sama7g5: add clock support for sama7g5
clk: at91: clk-utmi: add utmi support for sama7g5
clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs
clk: at91: add macro for pll ids mask
clk: at91: clk-programmable: add mux_table option
clk: at91: clk-peripheral: add support for changeable parent rate
clk: at91: clk-master: add master clock support for SAMA7G5
clk: at91: clk-generated: add mux_table option
clk: at91: clk-generated: pass the id of changeable parent at registration
clk: at91: replace conditional operator with double logical not
clk: at91: sckc: register slow_rc with accuracy option
clk: at91: sam9x60: fix main rc oscillator frequency
clk: at91: sam9x60-pll: use frac when setting frequency
clk: at91: sam9x60-pll: check fcore against ranges
clk: at91: sam9x60-pll: use logical or for range check
clk: at91: clk-sam9x60-pll: fix mul mask
clk: at91: clk-generated: check best_rate against ranges
clk: at91: clk-generated: continue if __clk_determine_rate() returns error
clk: at91: fix possible dead lock in new drivers
The function __clk_get_flags has not been used since the April 2019
commit a348f05361 ("ARM: omap2+: hwmod: drop CLK_IS_BASIC
flag usage"). Other uses were removed in June 2015, eg by
commit 98d8a60ecc ("clk: Convert __clk_get_flags() to
clk_hw_get_flags()"), which shows how clk_hw_get_flags can easily
be used instead.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/1596272022-14173-1-git-send-email-Julia.Lawall@inria.fr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
I copy/pasted these macros and forgot to update the argument
names and where they're passed to. Fix it so that these macros make
sense.
Reported-by: Maxime Ripard <maxime@cerno.tech>
Fixes: 194efb6e26 ("clk: gate: Add support for specifying parents via DT/pointers")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200325022257.148244-1-sboyd@kernel.org
Tested-by: Maxime Ripard <mripard@kernel.org>
- Support for Xilinx Versal platform clks
- Display clk controller on qcom sc7180
- Video clk controller on qcom sc7180
- Graphics clk controller on qcom sc7180
- CPU PLLs for qcom msm8916
- Fixes for clk controllers on qcom msm8998 SoCs
- Move qcom msm8974 gfx3d clk to RPM control
- Display port clk support on qcom sdm845 SoCs
- Global clk controller on qcom ipq6018
- Adjust composite clk to new way of describing clk parents
- Add a driver for BCLK of Freescale SAI cores
* clk-imx: (32 commits)
clk: imx: Add support for i.MX8MP clock driver
dt-bindings: imx: Add clock binding doc for i.MX8MP
clk: imx: gate4: Switch imx_clk_gate4_flags() to clk_hw based API
clk: imx: imx8mq: Switch to clk_hw based API
clk: imx: imx8mm: Switch to clk_hw based API
clk: imx: imx8mn: Switch to clk_hw based API
clk: imx: Remove __init for imx_obtain_fixed_clk_hw() API
clk: imx: gate3: Switch to clk_hw based API
clk: imx: add hw API imx_clk_hw_mux2_flags
clk: imx: add imx_unregister_hw_clocks
clk: imx: clk-composite-8m: Switch to clk_hw based API
clk: imx: clk-pll14xx: Switch to clk_hw based API
clk: imx7up: Rename the clks to hws
clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based
clk: imx: Rename the imx_clk_pfdv2 to imply it's clk_hw based
clk: imx: Rename the imx_clk_pllv4 to imply it's clk_hw based
clk: imx: Rename sccg and frac pll register to suggest clk_hw
clk: imx: imx7ulp composite: Rename to show is clk_hw based
clk: imx: pllv2: Switch to clk_hw based API
clk: imx: pllv1: Switch to clk_hw based API
...
* clk-ti:
clk: ti: clkctrl: Fix hidden dependency to node name
clk: ti: add clkctrl data dra7 sgx
clk: ti: omap5: Add missing AESS clock
clk: ti: dra7: fix parent for gmac_clkctrl
clk: ti: dra7: add vpe clkctrl data
clk: ti: dra7: add cam clkctrl data
dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock
* clk-xilinx:
clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flag
clk: zynqmp: Fix divider calculation
clk: zynqmp: Add support for get max divider
clk: zynqmp: Warn user if clock user are more than allowed
clk: zynqmp: Extend driver for versal
dt-bindings: clock: Add bindings for versal clock driver
* clk-nvidia:
clk: tegra20/30: Explicitly set parent clock for Video Decoder
clk: tegra20/30: Don't pre-initialize displays parent clock
clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()
clk: tegra: Mark fuse clock as critical
* clk-qcom: (35 commits)
clk: qcom: rpmh: Sort OF match table
dt-bindings: fix warnings in validation of qcom,gcc.yaml
dt-binding: fix compilation error of the example in qcom,gcc.yaml
clk: qcom: Add ipq6018 Global Clock Controller support
clk: qcom: Add DT bindings for ipq6018 gcc clock controller
clk: qcom: gcc-msm8996: Fix parent for CLKREF clocks
clk: qcom: rpmh: Add IPA clock for SC7180
clk: qcom: rpmh: skip undefined clocks when registering
clk: qcom: Add video clock controller driver for SC7180
dt-bindings: clock: Introduce SC7180 QCOM Video clock bindings
dt-bindings: clock: Add YAML schemas for the QCOM VIDEOCC clock bindings
clk: qcom: Add graphics clock controller driver for SC7180
dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindings
dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings
clk: qcom: apcs-msm8916: use clk_parent_data to specify the parent
clk: qcom: Add display clock controller driver for SC7180
dt-bindings: clock: Introduce QCOM sc7180 display clock bindings
dt-bindings: clock: Add YAML schemas for the QCOM DISPCC clock bindings
clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration
clk: qcom: alpha-pll: Remove useless read from set rate
...
* clk-freescale:
clk: fsl-sai: new driver
dt-bindings: clock: document the fsl-sai driver
clk: composite: add _register_composite_pdata() variants
* clk-qoriq:
clk: qoriq: add ls1088a hwaccel clocks support
clk: ls1028a: Add clock driver for Display output interface
dt/bindings: clk: Add YAML schemas for LS1028A Display Clock bindings
- Support dangerous debugfs actions on clks with dead code
- Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs
* clk-debugfs-danger:
clk: Add support for setting clk_rate via debugfs
* clk-basic-hw:
clk: divider: Add support for specifying parents via DT/pointers
clk: gate: Add support for specifying parents via DT/pointers
clk: mux: Add support for specifying parents via DT/pointers
clk: asm9260: Use parent accuracy in fixed rate clk
clk: fixed-rate: Document that accuracy isn't a rate
clk: fixed-rate: Add clk flags for parent accuracy
clk: fixed-rate: Add support for specifying parents via DT/pointers
clk: fixed-rate: Document accuracy member
clk: fixed-rate: Move to_clk_fixed_rate() to C file
clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy()
clk: fixed-rate: Convert to clk_hw based APIs
clk: gpio: Use DT way of specifying parents
* clk-renesas:
clk: renesas: Prepare for split of R-Car H3 config symbol
dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typo
clk: renesas: r7s9210: Add SPIBSC clock
clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
clk: renesas: Remove use of ARCH_R8A7796
clk: renesas: rcar-gen2: Change multipliers and dividers to u8
* clk-amlogic:
clk: clarify that clk_set_rate() does updates from top to bottom
clk: meson: meson8b: make the CCF use the glitch-free mali mux
clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
clk: meson: g12a: fix missing uart2 in regmap table
clk: meson: meson8b: use of_clk_hw_register to register the clocks
clk: meson: meson8b: don't register the XTAL clock when provided via OF
clk: meson: meson8b: change references to the XTAL clock to use [fw_]name
clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
dt-bindings: clock: meson8b: add the clock inputs
dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
* clk-allwinner:
clk: sunxi: a23/a33: Export the MIPI PLL
clk: sunxi: a31: Export the MIPI PLL
clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS
clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
clk: sunxi-ng: r40: Export MBUS clock
clk: sunxi: use of_device_get_match_data
Add support for the new way of specifying the clock parents. Add the
two new functions
clk_hw_register_composite_pdata()
clk_register_composite_pdata()
to let the driver provide parent_data instead of the parent_names.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lkml.kernel.org/r/20200102231101.11834-1-michael@walle.cc
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
After commit fc0c209c14 ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a divider clk with different
parent information. Then add a bunch of wrapper macros that only pass
down what needs to be passed down to the generic function to support
this with less arguments.
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-13-sboyd@kernel.org
[sboyd@kernel.org: Export __clk_hw_register_divider]
After commit fc0c209c14 ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a gate clk with different
parent information. Then add a bunch of wrapper macros that only pass
down what needs to be passed down to the generic function to support
this with less arguments.
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-12-sboyd@kernel.org
After commit fc0c209c14 ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a mux clk with different
parent information. Then add a bunch of wrapper macros that only pass
down what needs to be passed down to the generic function to support
this with less arguments.
Note: the msm drm driver passes an anonymous array through the macro
which seems to confuse my compiler. Adding a parenthesis around the
whole thing at the call site seems to fix it but it must be wrong. Maybe
it's better to split this patch and pick out the array bits there?
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-11-sboyd@kernel.org
Some clk providers want to use the accuracy of the parent clk and use
the fixed rate basic type clk to do that. This requires getting the
parent clk and extracting the accuracy before registering the fixed rate
clk. Let's add a flag for this and update the clk_ops to support this.
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-8-sboyd@kernel.org
After commit fc0c209c14 ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a fixed rate clk with
different parent information. Then add a bunch of wrapper macros that
only pass down what needs to be passed down to the generic function to
support this with less arguments.
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-7-sboyd@kernel.org
The only user of this macro is the fixed rate basic type. Move it there
to avoid polluting provider drivers.
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-5-sboyd@kernel.org
Nobody has used the gpio clk registration functions nor the gpio clk_ops
exposed by the basic gpio clk type. Let's remove all those APIs and move
the gpio clk support into the C file. Since nothing is using the
exported APIs, simplify the driver to be a platform driver that uses
clk_parent_data to pick 0th or 1st cell of the node's clocks property.
Cc: Simon Horman <horms@verge.net.au>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-2-sboyd@kernel.org
If the init callback is allowed to request resources, it needs a return
value to report the outcome of such a request.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190924123954.31561-3-jbrunet@baylibre.com
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This patch adds a new clk_hw_get_parent_index() function that can be
used to retrieve the index of a given clock's parent. This can be useful
for restoring a clock on system resume.
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
We don't want clk provider drivers to use the init structure after clk
registration time, but we leave a dangling reference to it by means of
clk_hw::init. Let's overwrite the member with NULL during clk_register()
so that this can't be used anymore after registration time.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-10-sboyd@kernel.org
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Introduce the clk_hw_set_parent() provider call to change parent of
a clock by using the clk_hw pointers.
This eases the clock reparenting from clock rate notifiers and
implementing DVFS with simpler code avoiding the boilerplates
functions as __clk_lookup(clk_hw_get_name()) then clk_set_parent().
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
- Support for CPU clks on Raspberry Pi devices
- Slow clk support for AT91 SAM9X60 SoCs
* clk-rpi-cpufreq:
clk: raspberrypi: register platform device for raspberrypi-cpufreq
firmware: raspberrypi: register clk device
clk: bcm283x: add driver interfacing with Raspberry Pi's firmware
clk: bcm2835: remove pllb
* clk-tegra:
clk: tegra: Do not enable PLL_RE_VCO on Tegra210
clk: tegra: Warn if an enabled PLL is in IDDQ
clk: tegra: Do not warn unnecessarily
clk: tegra210: fix PLLU and PLLU_OUT1
* clk-simplify-provider.h:
clk: consoldiate the __clk_get_hw() declarations
clk: Unexport __clk_of_table
clk: Remove ifdef for COMMON_CLK in clk-provider.h
* clk-sprd:
clk: sprd: Add check for return value of sprd_clk_regmap_init()
clk: sprd: Check error only for devm_regmap_init_mmio()
clk: sprd: Switch from of_iomap() to devm_ioremap_resource()
* clk-at91:
clk: at91: sckc: use dedicated functions to unregister clock
clk: at91: sckc: improve error path for sama5d4 sck registration
clk: at91: sckc: remove unnecessary line
clk: at91: sckc: improve error path for sam9x5 sck register
clk: at91: sckc: add support to free slow clock osclillator
clk: at91: sckc: add support to free slow rc oscillator
clk: at91: sckc: add support to free slow oscillator
clk: at91: sckc: add support for SAM9X60
dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller
clk: at91: sckc: add support to specify registers bit offsets
clk: at91: sckc: sama5d4 has no bypass support
Without this we were getting errors like:
In file included from drivers/clk/clkdev.c:22:0:
drivers/clk/clk.h:36:23: error: static declaration of '__clk_get_hw' follows non-static declaration
include/linux/clk-provider.h:808:16: note: previous declaration of '__clk_get_hw' was here
Fixes: 59fcdce425 ("clk: Remove ifdef for COMMON_CLK in clk-provider.h")
fixes: 73e0e496af ("clkdev: Always allocate a struct clk and call __clk_get() w/ CCF")
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
With the new clk parenting code, clk_init_data was expanded to include
.parent_data, for clk drivers to specify parents using a combination of
device tree clock-names, pointers to struct clk_hw, device tree clocks,
and/or fallback global clock names.
Add a new macro, CLK_FIXED_FACTOR_FW_NAME, that takes a string to match
a clock-names entry in the device tree to specify the clock parent.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw.
Add a new macro, CLK_FIXED_FACTOR_HWS, that can take an array of pointers
to struct clk_hw, instead of a string, as its parent. Taking an array
instead of a direct pointer allows the reuse of the array for multiple
clks, rather than having one compound literal with the same contents
allocated for each clk declaration.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw.
Add a new macro, CLK_FIXED_FACTOR_HW, that can take a struct clk_hw
pointer, instead of a string, as its parent.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
With the new clk parenting code, struct clk_init_data was expanded to
include .parent_data, for clk drivers that have parents referenced using
a combination of device tree clock-names, clock indices, and/or struct
clk_hw pointers.
Add a new macro that can take a list of struct clk_parent_data for
drivers to use.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
