linux-stable/tools/arch/x86/kcpuid/cpuid.csv

1	# The basic row format is:
2	# LEAF, SUBLEAF, register_name, bits, short_name, long_description
3	# Leaf 00H
4	0, 0, EAX, 31:0, max_basic_leafs, Max input value for supported subleafs
5	# Leaf 01H
6	1, 0, EAX, 3:0, stepping, Stepping ID
7	1, 0, EAX, 7:4, model, Model
8	1, 0, EAX, 11:8, family, Family ID
9	1, 0, EAX, 13:12, processor, Processor Type
10	1, 0, EAX, 19:16, model_ext, Extended Model ID
11	1, 0, EAX, 27:20, family_ext, Extended Family ID
12	1, 0, EBX, 7:0, brand, Brand Index
13	1, 0, EBX, 15:8, clflush_size, CLFLUSH line size (value * 8) in bytes
14	1, 0, EBX, 23:16, max_cpu_id, Maxim number of addressable logic cpu in this package
15	1, 0, EBX, 31:24, apic_id, Initial APIC ID
16	1, 0, ECX, 0, sse3, Streaming SIMD Extensions 3(SSE3)
17	1, 0, ECX, 1, pclmulqdq, PCLMULQDQ instruction supported
18	1, 0, ECX, 2, dtes64, DS area uses 64-bit layout
19	1, 0, ECX, 3, mwait, MONITOR/MWAIT supported
20	1, 0, ECX, 4, ds_cpl, CPL Qualified Debug Store which allows for branch message storage qualified by CPL
21	1, 0, ECX, 5, vmx, Virtual Machine Extensions supported
22	1, 0, ECX, 6, smx, Safer Mode Extension supported
23	1, 0, ECX, 7, eist, Enhanced Intel SpeedStep Technology
24	1, 0, ECX, 8, tm2, Thermal Monitor 2
25	1, 0, ECX, 9, ssse3, Supplemental Streaming SIMD Extensions 3 (SSSE3)
26	1, 0, ECX, 10, l1_ctx_id, L1 data cache could be set to either adaptive mode or shared mode (check IA32_MISC_ENABLE bit 24 definition)
27	1, 0, ECX, 11, sdbg, IA32_DEBUG_INTERFACE MSR for silicon debug supported
28	1, 0, ECX, 12, fma, FMA extensions using YMM state supported
29	1, 0, ECX, 13, cmpxchg16b, 'CMPXCHG16B - Compare and Exchange Bytes' supported
30	1, 0, ECX, 14, xtpr_update, xTPR Update Control supported
31	1, 0, ECX, 15, pdcm, Perfmon and Debug Capability present
32	1, 0, ECX, 17, pcid, Process-Context Identifiers feature present
33	1, 0, ECX, 18, dca, Prefetching data from a memory mapped device supported
34	1, 0, ECX, 19, sse4_1, SSE4.1 feature present
35	1, 0, ECX, 20, sse4_2, SSE4.2 feature present
36	1, 0, ECX, 21, x2apic, x2APIC supported
37	1, 0, ECX, 22, movbe, MOVBE instruction supported
38	1, 0, ECX, 23, popcnt, POPCNT instruction supported
39	1, 0, ECX, 24, tsc_deadline_timer, LAPIC supports one-shot operation using a TSC deadline value
40	1, 0, ECX, 25, aesni, AESNI instruction supported
41	1, 0, ECX, 26, xsave, XSAVE/XRSTOR processor extended states (XSETBV/XGETBV/XCR0)
42	1, 0, ECX, 27, osxsave, OS has set CR4.OSXSAVE bit to enable XSETBV/XGETBV/XCR0
43	1, 0, ECX, 28, avx, AVX instruction supported
44	1, 0, ECX, 29, f16c, 16-bit floating-point conversion instruction supported
45	1, 0, ECX, 30, rdrand, RDRAND instruction supported
46	1, 0, EDX, 0, fpu, x87 FPU on chip
47	1, 0, EDX, 1, vme, Virtual-8086 Mode Enhancement
48	1, 0, EDX, 2, de, Debugging Extensions
49	1, 0, EDX, 3, pse, Page Size Extensions
50	1, 0, EDX, 4, tsc, Time Stamp Counter
51	1, 0, EDX, 5, msr, RDMSR and WRMSR Support
52	1, 0, EDX, 6, pae, Physical Address Extensions
53	1, 0, EDX, 7, mce, Machine Check Exception
54	1, 0, EDX, 8, cx8, CMPXCHG8B instr
55	1, 0, EDX, 9, apic, APIC on Chip
56	1, 0, EDX, 11, sep, SYSENTER and SYSEXIT instrs
57	1, 0, EDX, 12, mtrr, Memory Type Range Registers
58	1, 0, EDX, 13, pge, Page Global Bit
59	1, 0, EDX, 14, mca, Machine Check Architecture
60	1, 0, EDX, 15, cmov, Conditional Move Instrs
61	1, 0, EDX, 16, pat, Page Attribute Table
62	1, 0, EDX, 17, pse36, 36-Bit Page Size Extension
63	1, 0, EDX, 18, psn, Processor Serial Number
64	1, 0, EDX, 19, clflush, CLFLUSH instr
65	# 1, 0, EDX, 20,
66	1, 0, EDX, 21, ds, Debug Store
67	1, 0, EDX, 22, acpi, Thermal Monitor and Software Controlled Clock Facilities
68	1, 0, EDX, 23, mmx, Intel MMX Technology
69	1, 0, EDX, 24, fxsr, XSAVE and FXRSTOR Instrs
70	1, 0, EDX, 25, sse, SSE
71	1, 0, EDX, 26, sse2, SSE2
72	1, 0, EDX, 27, ss, Self Snoop
73	1, 0, EDX, 28, hit, Max APIC IDs
74	1, 0, EDX, 29, tm, Thermal Monitor
75	# 1, 0, EDX, 30,
76	1, 0, EDX, 31, pbe, Pending Break Enable
77	# Leaf 02H
78	# cache and TLB descriptor info
79	# Leaf 03H
80	# Precessor Serial Number, introduced on Pentium III, not valid for
81	# latest models
82	# Leaf 04H
83	# thread/core and cache topology
84	4, 0, EAX, 4:0, cache_type, Cache type like instr/data or unified
85	4, 0, EAX, 7:5, cache_level, Cache Level (starts at 1)
86	4, 0, EAX, 8, cache_self_init, Cache Self Initialization
87	4, 0, EAX, 9, fully_associate, Fully Associative cache
88	# 4, 0, EAX, 13:10, resvd, resvd
89	4, 0, EAX, 25:14, max_logical_id, Max number of addressable IDs for logical processors sharing the cache
90	4, 0, EAX, 31:26, max_phy_id, Max number of addressable IDs for processors in phy package
91	4, 0, EBX, 11:0, cache_linesize, Size of a cache line in bytes
92	4, 0, EBX, 21:12, cache_partition, Physical Line partitions
93	4, 0, EBX, 31:22, cache_ways, Ways of associativity
94	4, 0, ECX, 31:0, cache_sets, Number of Sets - 1
95	4, 0, EDX, 0, c_wbinvd, 1 means WBINVD/INVD is not ganranteed to act upon lower level caches of non-originating threads sharing this cache
96	4, 0, EDX, 1, c_incl, Whether cache is inclusive of lower cache level
97	4, 0, EDX, 2, c_comp_index, Complex Cache Indexing
98	# Leaf 05H
99	# MONITOR/MWAIT
100	# Leaf 06H
101	# Thermal & Power Management
102	# Leaf 07H
103	# AVX512 refers to https://en.wikipedia.org/wiki/AVX-512
104	# XXX: Do we really need to enumerate each and every AVX512 sub features
105	# Leaf 08H
106	#
107	# Leaf 09H
108	# Direct Cache Access (DCA) information
109	# Leaf 0AH
110	# Architectural Performance Monitoring
111	#
112	# Do we really need to print out the PMU related stuff?
113	# Does normal user really care about it?
114	#
115	0xA, 0, EAX, 7:0, pmu_ver, Performance Monitoring Unit version
116	0xA, 0, EAX, 15:8, pmu_gp_cnt_num, Numer of general-purose PMU counters per logical CPU
117	0xA, 0, EAX, 23:16, pmu_cnt_bits, Bit wideth of PMU counter
118	0xA, 0, EAX, 31:24, pmu_ebx_bits, Length of EBX bit vector to enumerate PMU events
119	0xA, 0, EBX, 0, pmu_no_core_cycle_evt, Core cycle event not available
120	0xA, 0, EBX, 1, pmu_no_instr_ret_evt, Instruction retired event not available
121	0xA, 0, EBX, 2, pmu_no_ref_cycle_evt, Reference cycles event not available
122	0xA, 0, EBX, 3, pmu_no_llc_ref_evt, Last-level cache reference event not available
123	0xA, 0, EBX, 4, pmu_no_llc_mis_evt, Last-level cache misses event not available
124	0xA, 0, EBX, 5, pmu_no_br_instr_ret_evt, Branch instruction retired event not available
125	0xA, 0, EBX, 6, pmu_no_br_mispredict_evt, Branch mispredict retired event not available
126	0xA, 0, ECX, 4:0, pmu_fixed_cnt_num, Performance Monitoring Unit version
127	0xA, 0, ECX, 12:5, pmu_fixed_cnt_bits, Numer of PMU counters per logical CPU
128	# Leaf 0BH
129	# Extended Topology Enumeration Leaf
130	#
131	0xB, 0, EAX, 4:0, id_shift, Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type
132	0xB, 0, EBX, 15:0, cpu_nr, Number of logical processors at this level type
133	0xB, 0, ECX, 15:8, lvl_type, 0-Invalid 1-SMT 2-Core
134	0xB, 0, EDX, 31:0, x2apic_id, x2APIC ID the current logical processor
135	# Leaf 0DH
136	# Processor Extended State
137	0xD, 0, EAX, 0, x87, X87 state
138	0xD, 0, EAX, 1, sse, SSE state
139	0xD, 0, EAX, 2, avx, AVX state
140	0xD, 0, EAX, 4:3, mpx, MPX state
141	0xD, 0, EAX, 7:5, avx512, AVX-512 state
142	0xD, 0, EAX, 9, pkru, PKRU state
143	0xD, 0, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0
144	0xD, 0, ECX, 31:0, max_sz_xsave, Maximum size (bytes) of the XSAVE/XRSTOR save area
145	0xD, 1, EAX, 0, xsaveopt, XSAVEOPT available
146	0xD, 1, EAX, 1, xsavec, XSAVEC and compacted form supported
147	0xD, 1, EAX, 2, xgetbv, XGETBV supported
148	0xD, 1, EAX, 3, xsaves, XSAVES/XRSTORS and IA32_XSS supported
149	0xD, 1, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0
150	0xD, 1, ECX, 8, pt, PT state
151	0xD, 1, ECX, 11, cet_usr, CET user state
152	0xD, 1, ECX, 12, cet_supv, CET supervisor state
153	0xD, 1, ECX, 13, hdc, HDC state
154	0xD, 1, ECX, 16, hwp, HWP state
155	# Leaf 0FH
156	# Intel RDT Monitoring
157	0xF, 0, EBX, 31:0, rmid_range, Maximum range (zero-based) of RMID within this physical processor of all types
158	0xF, 0, EDX, 1, l3c_rdt_mon, L3 Cache RDT Monitoring supported
159	0xF, 1, ECX, 31:0, rmid_range, Maximum range (zero-based) of RMID of this types
160	0xF, 1, EDX, 0, l3c_ocp_mon, L3 Cache occupancy Monitoring supported
161	0xF, 1, EDX, 1, l3c_tbw_mon, L3 Cache Total Bandwidth Monitoring supported
162	0xF, 1, EDX, 2, l3c_lbw_mon, L3 Cache Local Bandwidth Monitoring supported
163	# Leaf 10H
164	# Intel RDT Allocation
165	0x10, 0, EBX, 1, l3c_rdt_alloc, L3 Cache Allocation supported
166	0x10, 0, EBX, 2, l2c_rdt_alloc, L2 Cache Allocation supported
167	0x10, 0, EBX, 3, mem_bw_alloc, Memory Bandwidth Allocation supported
168	# Leaf 12H
169	# SGX Capability
170	#
171	# Some detailed SGX features not added yet
172	0x12, 0, EAX, 0, sgx1, L3 Cache Allocation supported
173	0x12, 1, EAX, 0, sgx2, L3 Cache Allocation supported
174	# Leaf 14H
175	# Intel Processor Tracer
176	#
177	# Leaf 15H
178	# Time Stamp Counter and Nominal Core Crystal Clock Information
179	0x15, 0, EAX, 31:0, tsc_denominator, The denominator of the TSC/”core crystal clock” ratio
180	0x15, 0, EBX, 31:0, tsc_numerator, The numerator of the TSC/”core crystal clock” ratio
181	0x15, 0, ECX, 31:0, nom_freq, Nominal frequency of the core crystal clock in Hz
182	# Leaf 16H
183	# Processor Frequency Information
184	0x16, 0, EAX, 15:0, cpu_base_freq, Processor Base Frequency in MHz
185	0x16, 0, EBX, 15:0, cpu_max_freq, Maximum Frequency in MHz
186	0x16, 0, ECX, 15:0, bus_freq, Bus (Reference) Frequency in MHz
187	# Leaf 17H
188	# System-On-Chip Vendor Attribute
189	0x17, 0, EAX, 31:0, max_socid, Maximum input value of supported sub-leaf
190	0x17, 0, EBX, 15:0, soc_vid, SOC Vendor ID
191	0x17, 0, EBX, 16, std_vid, SOC Vendor ID is assigned via an industry standard scheme
192	0x17, 0, ECX, 31:0, soc_pid, SOC Project ID assigned by vendor
193	0x17, 0, EDX, 31:0, soc_sid, SOC Stepping ID
194	# Leaf 18H
195	# Deterministic Address Translation Parameters
196	# Leaf 19H
197	# Key Locker Leaf
198	# Leaf 1AH
199	# Hybrid Information
200	0x1A, 0, EAX, 31:24, core_type, 20H-Intel_Atom 40H-Intel_Core
201	# Leaf 1FH
202	# V2 Extended Topology - A preferred superset to leaf 0BH
203	# According to SDM
204	# 40000000H - 4FFFFFFFH is invalid range
205	# Leaf 80000001H
206	# Extended Processor Signature and Feature Bits
207	0x80000001, 0, EAX, 27:20, extfamily, Extended family
208	0x80000001, 0, EAX, 19:16, extmodel, Extended model
209	0x80000001, 0, EAX, 11:8, basefamily, Description of Family
210	0x80000001, 0, EAX, 11:8, basemodel, Model numbers vary with product
211	0x80000001, 0, EAX, 3:0, stepping, Processor stepping (revision) for a specific model
212	0x80000001, 0, EBX, 31:28, pkgtype, Specifies the package type
213	0x80000001, 0, ECX, 0, lahf_lm, LAHF/SAHF available in 64-bit mode
214	0x80000001, 0, ECX, 1, cmplegacy, Core multi-processing legacy mode
215	0x80000001, 0, ECX, 2, svm, Indicates support for: VMRUN, VMLOAD, VMSAVE, CLGI, VMMCALL, and INVLPGA
216	0x80000001, 0, ECX, 3, extapicspace, Extended APIC register space
217	0x80000001, 0, ECX, 4, altmovecr8, Indicates support for LOCK MOV CR0 means MOV CR8
218	0x80000001, 0, ECX, 5, lzcnt, LZCNT
219	0x80000001, 0, ECX, 6, sse4a, EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support
220	0x80000001, 0, ECX, 7, misalignsse, Misaligned SSE Mode
221	0x80000001, 0, ECX, 8, prefetchw, PREFETCHW
222	0x80000001, 0, ECX, 9, osvw, OS Visible Work-around support
223	0x80000001, 0, ECX, 10, ibs, Instruction Based Sampling
224	0x80000001, 0, ECX, 11, xop, Extended operation support
225	0x80000001, 0, ECX, 12, skinit, SKINIT and STGI support
226	0x80000001, 0, ECX, 13, wdt, Watchdog timer support
227	0x80000001, 0, ECX, 15, lwp, Lightweight profiling support
228	0x80000001, 0, ECX, 16, fma4, Four-operand FMA instruction support
229	0x80000001, 0, ECX, 17, tce, Translation cache extension
230	0x80000001, 0, ECX, 22, TopologyExtensions, Indicates support for Core::X86::Cpuid::CachePropEax0 and Core::X86::Cpuid::ExtApicId
231	0x80000001, 0, ECX, 23, perfctrextcore, Indicates support for Core::X86::Msr::PERF_CTL0 - 5 and Core::X86::Msr::PERF_CTR
232	0x80000001, 0, ECX, 24, perfctrextdf, Indicates support for Core::X86::Msr::DF_PERF_CTL and Core::X86::Msr::DF_PERF_CTR
233	0x80000001, 0, ECX, 26, databreakpointextension, Indicates data breakpoint support for Core::X86::Msr::DR0_ADDR_MASK, Core::X86::Msr::DR1_ADDR_MASK, Core::X86::Msr::DR2_ADDR_MASK and Core::X86::Msr::DR3_ADDR_MASK
234	0x80000001, 0, ECX, 27, perftsc, Performance time-stamp counter supported
235	0x80000001, 0, ECX, 28, perfctrextllc, Indicates support for L3 performance counter extensions
236	0x80000001, 0, ECX, 29, mwaitextended, MWAITX and MONITORX capability is supported
237	0x80000001, 0, ECX, 30, admskextn, Indicates support for address mask extension (to 32 bits and to all 4 DRs) for instruction breakpoints
238	0x80000001, 0, EDX, 0, fpu, x87 floating point unit on-chip
239	0x80000001, 0, EDX, 1, vme, Virtual-mode enhancements
240	0x80000001, 0, EDX, 2, de, Debugging extensions, IO breakpoints, CR4.DE
241	0x80000001, 0, EDX, 3, pse, Page-size extensions (4 MB pages)
242	0x80000001, 0, EDX, 4, tsc, Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD
243	0x80000001, 0, EDX, 5, msr, Model-specific registers (MSRs), with RDMSR and WRMSR instructions
244	0x80000001, 0, EDX, 6, pae, Physical-address extensions (PAE)
245	0x80000001, 0, EDX, 7, mce, Machine Check Exception, CR4.MCE
246	0x80000001, 0, EDX, 8, cmpxchg8b, CMPXCHG8B instruction
247	0x80000001, 0, EDX, 9, apic, advanced programmable interrupt controller (APIC) exists and is enabled
248	0x80000001, 0, EDX, 11, sysret, SYSCALL/SYSRET supported
249	0x80000001, 0, EDX, 12, mtrr, Memory-type range registers
250	0x80000001, 0, EDX, 13, pge, Page global extension, CR4.PGE
251	0x80000001, 0, EDX, 14, mca, Machine check architecture, MCG_CAP
252	0x80000001, 0, EDX, 15, cmov, Conditional move instructions, CMOV, FCOMI, FCMOV
253	0x80000001, 0, EDX, 16, pat, Page attribute table
254	0x80000001, 0, EDX, 17, pse36, Page-size extensions
255	0x80000001, 0, EDX, 20, exec_dis, Execute Disable Bit available
256	0x80000001, 0, EDX, 22, mmxext, AMD extensions to MMX instructions
257	0x80000001, 0, EDX, 23, mmx, MMX instructions
258	0x80000001, 0, EDX, 24, fxsr, FXSAVE and FXRSTOR instructions
259	0x80000001, 0, EDX, 25, ffxsr, FXSAVE and FXRSTOR instruction optimizations
260	0x80000001, 0, EDX, 26, 1gb_page, 1GB page supported
261	0x80000001, 0, EDX, 27, rdtscp, RDTSCP and IA32_TSC_AUX are available
262	0x80000001, 0, EDX, 29, lm, 64b Architecture supported
263	0x80000001, 0, EDX, 30, threednowext, AMD extensions to 3DNow! instructions
264	0x80000001, 0, EDX, 31, threednow, 3DNow! instructions
265	# Leaf 80000002H/80000003H/80000004H
266	# Processor Brand String
267	# Leaf 80000005H
268	# Reserved
269	# Leaf 80000006H
270	# Extended L2 Cache Features
271	0x80000006, 0, ECX, 7:0, clsize, Cache Line size in bytes
272	0x80000006, 0, ECX, 15:12, l2c_assoc, L2 Associativity
273	0x80000006, 0, ECX, 31:16, csize, Cache size in 1K units
274	# Leaf 80000007H
275	0x80000007, 0, EDX, 8, nonstop_tsc, Invariant TSC available
276	# Leaf 80000008H
277	0x80000008, 0, EAX, 7:0, phy_adr_bits, Physical Address Bits
278	0x80000008, 0, EAX, 15:8, lnr_adr_bits, Linear Address Bits
279	0x80000007, 0, EBX, 9, wbnoinvd, WBNOINVD
280	# 0x8000001E
281	# EAX: Extended APIC ID
282	# EBX: Core Identifiers
283	# ECX: Node Identifiers
284	# 8000001F: AMD Secure Encryption