linux-stable/arch/xtensa
Max Filippov 61f6ecb758 xtensa: add missing isync to the cpu_reset TLB code
commit cd8869f4cb upstream.

ITLB entry modifications must be followed by the isync instruction
before the new entries are possibly used. cpu_reset lacks one isync
between ITLB way 6 initialization and jump to the identity mapping.
Add missing isync to xtensa cpu_reset.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-08-25 10:47:47 +02:00
..
boot xtensa: xtfpga.dtsi: fix dtc warnings about SPI 2019-02-12 19:47:05 +01:00
configs xtensa: smp_lx200_defconfig: fix vectors clash 2019-03-13 14:02:28 -07:00
include xtensa: make sure bFLT stack is 16 byte aligned 2018-11-21 09:19:16 +01:00
kernel xtensa: add missing isync to the cpu_reset TLB code 2019-08-25 10:47:47 +02:00
lib xtensa: add support for KASAN 2017-12-16 22:37:12 -08:00
mm mm: convert return type of handle_mm_fault() caller to vm_fault_t 2018-08-17 16:20:28 -07:00
oprofile License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
platforms xtensa: ISS: don't allocate memory in platform_setup 2018-09-06 11:29:31 -07:00
variants xtensa: add test_kc705_be variant 2018-08-20 12:34:45 -07:00
Kconfig xtensa: enable SG chaining in Kconfig 2018-09-11 22:12:59 -07:00
Kconfig.debug Kconfig: consolidate the "Kernel hacking" menu 2018-08-02 08:06:48 +09:00
Makefile xtensa: remove unnecessary KBUILD_SRC ifeq conditional 2018-09-11 22:09:48 -07:00