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![Doug Brown](/assets/img/avatar_default.png)
Older GC300 revisions have their power registers at an offset of 0x200 rather than 0x100. Add new gpu_read_power and gpu_write_power functions to encapsulate accesses to the power addresses and fix the addresses. Signed-off-by: Doug Brown <doug@schmorgal.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
207 lines
4.7 KiB
C
207 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015-2018 Etnaviv Project
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*/
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#ifndef __ETNAVIV_GPU_H__
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#define __ETNAVIV_GPU_H__
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#include "etnaviv_cmdbuf.h"
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#include "etnaviv_gem.h"
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#include "etnaviv_mmu.h"
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#include "etnaviv_drv.h"
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#include "common.xml.h"
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struct etnaviv_gem_submit;
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struct etnaviv_vram_mapping;
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struct etnaviv_chip_identity {
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u32 model;
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u32 revision;
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u32 product_id;
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u32 customer_id;
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u32 eco_id;
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/* Supported feature fields. */
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u32 features;
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/* Supported minor feature fields. */
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u32 minor_features0;
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u32 minor_features1;
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u32 minor_features2;
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u32 minor_features3;
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u32 minor_features4;
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u32 minor_features5;
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u32 minor_features6;
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u32 minor_features7;
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u32 minor_features8;
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u32 minor_features9;
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u32 minor_features10;
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u32 minor_features11;
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/* Number of streams supported. */
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u32 stream_count;
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/* Total number of temporary registers per thread. */
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u32 register_max;
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/* Maximum number of threads. */
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u32 thread_count;
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/* Number of shader cores. */
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u32 shader_core_count;
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/* Size of the vertex cache. */
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u32 vertex_cache_size;
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/* Number of entries in the vertex output buffer. */
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u32 vertex_output_buffer_size;
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/* Number of pixel pipes. */
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u32 pixel_pipes;
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/* Number of instructions. */
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u32 instruction_count;
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/* Number of constants. */
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u32 num_constants;
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/* Buffer size */
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u32 buffer_size;
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/* Number of varyings */
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u8 varyings_count;
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};
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enum etnaviv_sec_mode {
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ETNA_SEC_NONE = 0,
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ETNA_SEC_KERNEL,
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ETNA_SEC_TZ
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};
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struct etnaviv_event {
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struct dma_fence *fence;
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struct etnaviv_gem_submit *submit;
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void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
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};
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struct etnaviv_cmdbuf_suballoc;
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struct regulator;
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struct clk;
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#define ETNA_NR_EVENTS 30
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struct etnaviv_gpu {
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struct drm_device *drm;
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struct thermal_cooling_device *cooling;
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struct device *dev;
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struct mutex lock;
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struct etnaviv_chip_identity identity;
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enum etnaviv_sec_mode sec_mode;
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struct workqueue_struct *wq;
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struct drm_gpu_scheduler sched;
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bool initialized;
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bool fe_running;
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/* 'ring'-buffer: */
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struct etnaviv_cmdbuf buffer;
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int exec_state;
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/* event management: */
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DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
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struct etnaviv_event event[ETNA_NR_EVENTS];
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struct completion event_free;
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spinlock_t event_spinlock;
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u32 idle_mask;
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/* Fencing support */
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struct mutex fence_lock;
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struct idr fence_idr;
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u32 next_fence;
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u32 completed_fence;
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wait_queue_head_t fence_event;
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u64 fence_context;
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spinlock_t fence_spinlock;
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/* worker for handling 'sync' points: */
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struct work_struct sync_point_work;
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int sync_point_event;
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/* hang detection */
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u32 hangcheck_dma_addr;
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u32 hangcheck_fence;
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void __iomem *mmio;
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int irq;
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struct etnaviv_iommu_context *mmu_context;
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unsigned int flush_seq;
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/* Power Control: */
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struct clk *clk_bus;
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struct clk *clk_reg;
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struct clk *clk_core;
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struct clk *clk_shader;
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unsigned int freq_scale;
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unsigned long base_rate_core;
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unsigned long base_rate_shader;
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};
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static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
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{
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writel(data, gpu->mmio + reg);
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}
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static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
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{
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return readl(gpu->mmio + reg);
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}
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static inline u32 gpu_fix_power_address(struct etnaviv_gpu *gpu, u32 reg)
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{
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/* Power registers in GC300 < 2.0 are offset by 0x100 */
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if (gpu->identity.model == chipModel_GC300 &&
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gpu->identity.revision < 0x2000)
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reg += 0x100;
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return reg;
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}
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static inline void gpu_write_power(struct etnaviv_gpu *gpu, u32 reg, u32 data)
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{
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writel(data, gpu->mmio + gpu_fix_power_address(gpu, reg));
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}
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static inline u32 gpu_read_power(struct etnaviv_gpu *gpu, u32 reg)
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{
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return readl(gpu->mmio + gpu_fix_power_address(gpu, reg));
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}
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int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
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int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
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bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
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#ifdef CONFIG_DEBUG_FS
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int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
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#endif
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void etnaviv_gpu_recover_hang(struct etnaviv_gem_submit *submit);
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void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
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int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
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u32 fence, struct drm_etnaviv_timespec *timeout);
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int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
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struct etnaviv_gem_object *etnaviv_obj,
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struct drm_etnaviv_timespec *timeout);
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struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit);
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int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
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void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
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int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
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void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
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extern struct platform_driver etnaviv_gpu_driver;
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#endif /* __ETNAVIV_GPU_H__ */
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