Levin Du 0aa49a4ddc clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 ... [ Upstream commit 640332d1a0 ] PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave from power on and the VDD_LOG is about 0.9V. When the kernel boots normally into the system, the PWM2 keeps outputing PWM signal. But the kernel hangs randomly after "Starting kernel ..." line on that board. When it happens, PWM2 outputs high level which causes VDD_LOG drops to 0.4V below the normal operating voltage. By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array, PWM clock is ensured to be prepared at startup and the PWM2 output is normal. After repeated tests, the early boot hang is gone. This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards. Signed-off-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2018-09-15 09:45:32 +02:00
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clk-cpu.c	clk: rockchip: validity should be checked prior to cpu clock rate change	2016-11-14 12:20:53 +01:00
clk-ddr.c	clk: rockchip: don't return NULL when failing to register ddrclk branch	2016-10-16 02:39:58 +02:00
clk-inverter.c	clk: rockchip: don't return NULL when registering inverter fails	2016-02-15 23:35:20 +01:00
clk-mmc-phase.c	clk: rockchip: Prevent calculating mmc phase if clock rate is zero	2018-05-25 16:17:53 +02:00
clk-muxgrf.c	clk: rockchip: add a clock-type for muxes based in the grf	2017-01-02 14:24:57 +01:00
clk-pll.c	clk: rockchip: add pll_wait_lock for pll_enable	2017-03-22 18:33:22 +01:00
clk-rk3036.c	clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036	2017-06-02 15:42:38 +02:00
clk-rk3128.c	clk: rockchip: add sclk_timer5 as critical clock on rk3128	2017-09-17 01:55:36 +02:00
clk-rk3188.c	clk: rockchip: use clock ids for memory controller parts on rk3066/rk3188	2017-01-13 17:32:55 +01:00
clk-rk3228.c	clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228	2018-05-25 16:17:52 +02:00
clk-rk3288.c	clk: rockchip: mark noc and some special clk as critical on rk3288	2017-06-02 15:54:20 +02:00
clk-rk3328.c	clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328	2017-03-10 11:20:02 +01:00
clk-rk3368.c	clk: rockchip: mark some special clk as critical on rk3368	2017-06-02 15:57:32 +02:00
clk-rk3399.c	clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399	2018-09-15 09:45:32 +02:00
clk-rockchip.c	clk: rockchip: handle of_iomap failures in legacy clock driver	2016-08-23 18:00:25 +02:00
clk-rv1108.c	clk: rockchip: fix the rv1108 clk_mac sel register description	2017-08-22 02:55:03 +02:00
clk.c	clk: rockchip: Mark rockchip_fractional_approximation static	2017-08-23 15:35:41 -07:00
clk.h	clk: rockchip: rename RK1108 to RV1108	2017-03-22 18:03:04 +01:00
Makefile	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
softrst.c	clk: rockchip: Make reset_control_ops const	2016-03-29 16:29:46 -07:00