Weihao Li 8c83431277 clk: rockchip: rk3128: Fix HCLK_OTG gate register ... [ Upstream commit c6c5a5580d ] The HCLK_OTG gate control is in CRU_CLKGATE5_CON, not CRU_CLKGATE3_CON. Signed-off-by: Weihao Li <cn.liweihao@gmail.com> Link: https://lore.kernel.org/r/20231031111816.8777-1-cn.liweihao@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Sasha Levin <sashal@kernel.org>		2024-01-20 11:51:42 +01:00
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clk-cpu.c
clk-ddr.c
clk-half-divider.c
clk-inverter.c
clk-mmc-phase.c
clk-muxgrf.c
clk-pll.c
clk-px30.c
clk-rk3036.c
clk-rk3128.c	clk: rockchip: rk3128: Fix HCLK_OTG gate register	2024-01-20 11:51:42 +01:00
clk-rk3188.c
clk-rk3228.c
clk-rk3288.c
clk-rk3308.c
clk-rk3328.c
clk-rk3368.c
clk-rk3399.c
clk-rk3568.c	clk: rockchip: rk3568: Add PLL rate for 292.5MHz	2024-01-20 11:51:42 +01:00
clk-rk3588.c
clk-rv1108.c
clk-rv1126.c	Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next	2023-08-30 14:38:19 -07:00
clk.c
clk.h
Kconfig
Makefile
rst-rk3588.c
softrst.c