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![Kedareswara rao Appana](/assets/img/avatar_default.png)
This patch adds xilinx CAN controller support. This driver supports both ZYNQ CANPS and Soft IP AXI CAN controller. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
1208 lines
34 KiB
C
1208 lines
34 KiB
C
/* Xilinx CAN device driver
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*
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* Copyright (C) 2012 - 2014 Xilinx, Inc.
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* Copyright (C) 2009 PetaLogix. All rights reserved.
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*
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* Description:
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* This driver is developed for Axi CAN IP and for Zynq CANPS Controller.
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/skbuff.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/can/dev.h>
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#include <linux/can/error.h>
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#include <linux/can/led.h>
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#define DRIVER_NAME "xilinx_can"
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/* CAN registers set */
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enum xcan_reg {
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XCAN_SRR_OFFSET = 0x00, /* Software reset */
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XCAN_MSR_OFFSET = 0x04, /* Mode select */
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XCAN_BRPR_OFFSET = 0x08, /* Baud rate prescaler */
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XCAN_BTR_OFFSET = 0x0C, /* Bit timing */
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XCAN_ECR_OFFSET = 0x10, /* Error counter */
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XCAN_ESR_OFFSET = 0x14, /* Error status */
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XCAN_SR_OFFSET = 0x18, /* Status */
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XCAN_ISR_OFFSET = 0x1C, /* Interrupt status */
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XCAN_IER_OFFSET = 0x20, /* Interrupt enable */
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XCAN_ICR_OFFSET = 0x24, /* Interrupt clear */
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XCAN_TXFIFO_ID_OFFSET = 0x30,/* TX FIFO ID */
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XCAN_TXFIFO_DLC_OFFSET = 0x34, /* TX FIFO DLC */
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XCAN_TXFIFO_DW1_OFFSET = 0x38, /* TX FIFO Data Word 1 */
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XCAN_TXFIFO_DW2_OFFSET = 0x3C, /* TX FIFO Data Word 2 */
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XCAN_RXFIFO_ID_OFFSET = 0x50, /* RX FIFO ID */
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XCAN_RXFIFO_DLC_OFFSET = 0x54, /* RX FIFO DLC */
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XCAN_RXFIFO_DW1_OFFSET = 0x58, /* RX FIFO Data Word 1 */
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XCAN_RXFIFO_DW2_OFFSET = 0x5C, /* RX FIFO Data Word 2 */
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};
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/* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
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#define XCAN_SRR_CEN_MASK 0x00000002 /* CAN enable */
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#define XCAN_SRR_RESET_MASK 0x00000001 /* Soft Reset the CAN core */
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#define XCAN_MSR_LBACK_MASK 0x00000002 /* Loop back mode select */
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#define XCAN_MSR_SLEEP_MASK 0x00000001 /* Sleep mode select */
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#define XCAN_BRPR_BRP_MASK 0x000000FF /* Baud rate prescaler */
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#define XCAN_BTR_SJW_MASK 0x00000180 /* Synchronous jump width */
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#define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
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#define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
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#define XCAN_ECR_REC_MASK 0x0000FF00 /* Receive error counter */
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#define XCAN_ECR_TEC_MASK 0x000000FF /* Transmit error counter */
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#define XCAN_ESR_ACKER_MASK 0x00000010 /* ACK error */
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#define XCAN_ESR_BERR_MASK 0x00000008 /* Bit error */
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#define XCAN_ESR_STER_MASK 0x00000004 /* Stuff error */
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#define XCAN_ESR_FMER_MASK 0x00000002 /* Form error */
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#define XCAN_ESR_CRCER_MASK 0x00000001 /* CRC error */
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#define XCAN_SR_TXFLL_MASK 0x00000400 /* TX FIFO is full */
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#define XCAN_SR_ESTAT_MASK 0x00000180 /* Error status */
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#define XCAN_SR_ERRWRN_MASK 0x00000040 /* Error warning */
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#define XCAN_SR_NORMAL_MASK 0x00000008 /* Normal mode */
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#define XCAN_SR_LBACK_MASK 0x00000002 /* Loop back mode */
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#define XCAN_SR_CONFIG_MASK 0x00000001 /* Configuration mode */
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#define XCAN_IXR_TXFEMP_MASK 0x00004000 /* TX FIFO Empty */
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#define XCAN_IXR_WKUP_MASK 0x00000800 /* Wake up interrupt */
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#define XCAN_IXR_SLP_MASK 0x00000400 /* Sleep interrupt */
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#define XCAN_IXR_BSOFF_MASK 0x00000200 /* Bus off interrupt */
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#define XCAN_IXR_ERROR_MASK 0x00000100 /* Error interrupt */
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#define XCAN_IXR_RXNEMP_MASK 0x00000080 /* RX FIFO NotEmpty intr */
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#define XCAN_IXR_RXOFLW_MASK 0x00000040 /* RX FIFO Overflow intr */
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#define XCAN_IXR_RXOK_MASK 0x00000010 /* Message received intr */
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#define XCAN_IXR_TXFLL_MASK 0x00000004 /* Tx FIFO Full intr */
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#define XCAN_IXR_TXOK_MASK 0x00000002 /* TX successful intr */
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#define XCAN_IXR_ARBLST_MASK 0x00000001 /* Arbitration lost intr */
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#define XCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
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#define XCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
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#define XCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
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#define XCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
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#define XCAN_IDR_RTR_MASK 0x00000001 /* Remote TX request */
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#define XCAN_DLCR_DLC_MASK 0xF0000000 /* Data length code */
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#define XCAN_INTR_ALL (XCAN_IXR_TXOK_MASK | XCAN_IXR_BSOFF_MASK |\
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XCAN_IXR_WKUP_MASK | XCAN_IXR_SLP_MASK | \
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XCAN_IXR_RXNEMP_MASK | XCAN_IXR_ERROR_MASK | \
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XCAN_IXR_ARBLST_MASK | XCAN_IXR_RXOK_MASK)
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/* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
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#define XCAN_BTR_SJW_SHIFT 7 /* Synchronous jump width */
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#define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
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#define XCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
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#define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
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#define XCAN_DLCR_DLC_SHIFT 28 /* Data length code */
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#define XCAN_ESR_REC_SHIFT 8 /* Rx Error Count */
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/* CAN frame length constants */
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#define XCAN_FRAME_MAX_DATA_LEN 8
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#define XCAN_TIMEOUT (1 * HZ)
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/**
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* struct xcan_priv - This definition define CAN driver instance
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* @can: CAN private data structure.
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* @tx_head: Tx CAN packets ready to send on the queue
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* @tx_tail: Tx CAN packets successfully sended on the queue
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* @tx_max: Maximum number packets the driver can send
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* @napi: NAPI structure
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* @read_reg: For reading data from CAN registers
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* @write_reg: For writing data to CAN registers
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* @dev: Network device data structure
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* @reg_base: Ioremapped address to registers
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* @irq_flags: For request_irq()
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* @bus_clk: Pointer to struct clk
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* @can_clk: Pointer to struct clk
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*/
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struct xcan_priv {
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struct can_priv can;
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unsigned int tx_head;
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unsigned int tx_tail;
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unsigned int tx_max;
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struct napi_struct napi;
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u32 (*read_reg)(const struct xcan_priv *priv, enum xcan_reg reg);
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void (*write_reg)(const struct xcan_priv *priv, enum xcan_reg reg,
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u32 val);
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struct net_device *dev;
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void __iomem *reg_base;
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unsigned long irq_flags;
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struct clk *bus_clk;
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struct clk *can_clk;
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};
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/* CAN Bittiming constants as per Xilinx CAN specs */
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static const struct can_bittiming_const xcan_bittiming_const = {
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.name = DRIVER_NAME,
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.tseg1_min = 1,
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.tseg1_max = 16,
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.tseg2_min = 1,
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.tseg2_max = 8,
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.sjw_max = 4,
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.brp_min = 1,
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.brp_max = 256,
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.brp_inc = 1,
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};
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/**
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* xcan_write_reg_le - Write a value to the device register little endian
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* @priv: Driver private data structure
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* @reg: Register offset
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* @val: Value to write at the Register offset
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*
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* Write data to the paricular CAN register
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*/
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static void xcan_write_reg_le(const struct xcan_priv *priv, enum xcan_reg reg,
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u32 val)
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{
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iowrite32(val, priv->reg_base + reg);
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}
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/**
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* xcan_read_reg_le - Read a value from the device register little endian
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* @priv: Driver private data structure
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* @reg: Register offset
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*
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* Read data from the particular CAN register
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* Return: value read from the CAN register
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*/
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static u32 xcan_read_reg_le(const struct xcan_priv *priv, enum xcan_reg reg)
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{
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return ioread32(priv->reg_base + reg);
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}
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/**
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* xcan_write_reg_be - Write a value to the device register big endian
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* @priv: Driver private data structure
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* @reg: Register offset
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* @val: Value to write at the Register offset
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*
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* Write data to the paricular CAN register
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*/
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static void xcan_write_reg_be(const struct xcan_priv *priv, enum xcan_reg reg,
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u32 val)
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{
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iowrite32be(val, priv->reg_base + reg);
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}
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/**
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* xcan_read_reg_be - Read a value from the device register big endian
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* @priv: Driver private data structure
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* @reg: Register offset
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*
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* Read data from the particular CAN register
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* Return: value read from the CAN register
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*/
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static u32 xcan_read_reg_be(const struct xcan_priv *priv, enum xcan_reg reg)
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{
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return ioread32be(priv->reg_base + reg);
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}
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/**
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* set_reset_mode - Resets the CAN device mode
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* @ndev: Pointer to net_device structure
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*
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* This is the driver reset mode routine.The driver
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* enters into configuration mode.
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*
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* Return: 0 on success and failure value on error
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*/
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static int set_reset_mode(struct net_device *ndev)
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{
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struct xcan_priv *priv = netdev_priv(ndev);
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unsigned long timeout;
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priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
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timeout = jiffies + XCAN_TIMEOUT;
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while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) {
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if (time_after(jiffies, timeout)) {
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netdev_warn(ndev, "timed out for config mode\n");
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return -ETIMEDOUT;
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}
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usleep_range(500, 10000);
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}
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return 0;
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}
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/**
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* xcan_set_bittiming - CAN set bit timing routine
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* @ndev: Pointer to net_device structure
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*
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* This is the driver set bittiming routine.
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* Return: 0 on success and failure value on error
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*/
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static int xcan_set_bittiming(struct net_device *ndev)
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{
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struct xcan_priv *priv = netdev_priv(ndev);
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struct can_bittiming *bt = &priv->can.bittiming;
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u32 btr0, btr1;
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u32 is_config_mode;
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/* Check whether Xilinx CAN is in configuration mode.
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* It cannot set bit timing if Xilinx CAN is not in configuration mode.
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*/
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is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) &
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XCAN_SR_CONFIG_MASK;
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if (!is_config_mode) {
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netdev_alert(ndev,
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"BUG! Cannot set bittiming - CAN is not in config mode\n");
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return -EPERM;
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}
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/* Setting Baud Rate prescalar value in BRPR Register */
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btr0 = (bt->brp - 1);
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/* Setting Time Segment 1 in BTR Register */
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btr1 = (bt->prop_seg + bt->phase_seg1 - 1);
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/* Setting Time Segment 2 in BTR Register */
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btr1 |= (bt->phase_seg2 - 1) << XCAN_BTR_TS2_SHIFT;
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/* Setting Synchronous jump width in BTR Register */
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btr1 |= (bt->sjw - 1) << XCAN_BTR_SJW_SHIFT;
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priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0);
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priv->write_reg(priv, XCAN_BTR_OFFSET, btr1);
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netdev_dbg(ndev, "BRPR=0x%08x, BTR=0x%08x\n",
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priv->read_reg(priv, XCAN_BRPR_OFFSET),
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priv->read_reg(priv, XCAN_BTR_OFFSET));
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return 0;
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}
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/**
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* xcan_chip_start - This the drivers start routine
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* @ndev: Pointer to net_device structure
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*
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* This is the drivers start routine.
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* Based on the State of the CAN device it puts
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* the CAN device into a proper mode.
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*
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* Return: 0 on success and failure value on error
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*/
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static int xcan_chip_start(struct net_device *ndev)
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{
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struct xcan_priv *priv = netdev_priv(ndev);
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u32 err, reg_msr, reg_sr_mask;
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unsigned long timeout;
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/* Check if it is in reset mode */
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err = set_reset_mode(ndev);
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if (err < 0)
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return err;
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err = xcan_set_bittiming(ndev);
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if (err < 0)
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return err;
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/* Enable interrupts */
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priv->write_reg(priv, XCAN_IER_OFFSET, XCAN_INTR_ALL);
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/* Check whether it is loopback mode or normal mode */
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if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
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reg_msr = XCAN_MSR_LBACK_MASK;
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reg_sr_mask = XCAN_SR_LBACK_MASK;
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} else {
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reg_msr = 0x0;
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reg_sr_mask = XCAN_SR_NORMAL_MASK;
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}
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priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr);
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priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
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timeout = jiffies + XCAN_TIMEOUT;
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while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & reg_sr_mask)) {
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if (time_after(jiffies, timeout)) {
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netdev_warn(ndev,
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"timed out for correct mode\n");
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return -ETIMEDOUT;
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}
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}
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netdev_dbg(ndev, "status:#x%08x\n",
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priv->read_reg(priv, XCAN_SR_OFFSET));
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priv->can.state = CAN_STATE_ERROR_ACTIVE;
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return 0;
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}
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/**
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* xcan_do_set_mode - This sets the mode of the driver
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* @ndev: Pointer to net_device structure
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* @mode: Tells the mode of the driver
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*
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* This check the drivers state and calls the
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* the corresponding modes to set.
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*
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* Return: 0 on success and failure value on error
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*/
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static int xcan_do_set_mode(struct net_device *ndev, enum can_mode mode)
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{
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int ret;
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switch (mode) {
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case CAN_MODE_START:
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ret = xcan_chip_start(ndev);
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if (ret < 0) {
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netdev_err(ndev, "xcan_chip_start failed!\n");
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return ret;
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}
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netif_wake_queue(ndev);
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break;
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default:
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ret = -EOPNOTSUPP;
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break;
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}
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return ret;
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}
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/**
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* xcan_start_xmit - Starts the transmission
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* @skb: sk_buff pointer that contains data to be Txed
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* @ndev: Pointer to net_device structure
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*
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* This function is invoked from upper layers to initiate transmission. This
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* function uses the next available free txbuff and populates their fields to
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* start the transmission.
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*
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* Return: 0 on success and failure value on error
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*/
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static int xcan_start_xmit(struct sk_buff *skb, struct net_device *ndev)
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{
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struct xcan_priv *priv = netdev_priv(ndev);
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struct net_device_stats *stats = &ndev->stats;
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struct can_frame *cf = (struct can_frame *)skb->data;
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u32 id, dlc, data[2] = {0, 0};
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if (can_dropped_invalid_skb(ndev, skb))
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return NETDEV_TX_OK;
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/* Check if the TX buffer is full */
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if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) &
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XCAN_SR_TXFLL_MASK)) {
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netif_stop_queue(ndev);
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netdev_err(ndev, "BUG!, TX FIFO full when queue awake!\n");
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return NETDEV_TX_BUSY;
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}
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/* Watch carefully on the bit sequence */
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if (cf->can_id & CAN_EFF_FLAG) {
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/* Extended CAN ID format */
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id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) &
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XCAN_IDR_ID2_MASK;
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id |= (((cf->can_id & CAN_EFF_MASK) >>
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(CAN_EFF_ID_BITS-CAN_SFF_ID_BITS)) <<
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XCAN_IDR_ID1_SHIFT) & XCAN_IDR_ID1_MASK;
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/* The substibute remote TX request bit should be "1"
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* for extended frames as in the Xilinx CAN datasheet
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*/
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id |= XCAN_IDR_IDE_MASK | XCAN_IDR_SRR_MASK;
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if (cf->can_id & CAN_RTR_FLAG)
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/* Extended frames remote TX request */
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id |= XCAN_IDR_RTR_MASK;
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} else {
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/* Standard CAN ID format */
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id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) &
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XCAN_IDR_ID1_MASK;
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if (cf->can_id & CAN_RTR_FLAG)
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/* Standard frames remote TX request */
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id |= XCAN_IDR_SRR_MASK;
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}
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dlc = cf->can_dlc << XCAN_DLCR_DLC_SHIFT;
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if (cf->can_dlc > 0)
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data[0] = be32_to_cpup((__be32 *)(cf->data + 0));
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if (cf->can_dlc > 4)
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data[1] = be32_to_cpup((__be32 *)(cf->data + 4));
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|
|
can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max);
|
|
priv->tx_head++;
|
|
|
|
/* Write the Frame to Xilinx CAN TX FIFO */
|
|
priv->write_reg(priv, XCAN_TXFIFO_ID_OFFSET, id);
|
|
/* If the CAN frame is RTR frame this write triggers tranmission */
|
|
priv->write_reg(priv, XCAN_TXFIFO_DLC_OFFSET, dlc);
|
|
if (!(cf->can_id & CAN_RTR_FLAG)) {
|
|
priv->write_reg(priv, XCAN_TXFIFO_DW1_OFFSET, data[0]);
|
|
/* If the CAN frame is Standard/Extended frame this
|
|
* write triggers tranmission
|
|
*/
|
|
priv->write_reg(priv, XCAN_TXFIFO_DW2_OFFSET, data[1]);
|
|
stats->tx_bytes += cf->can_dlc;
|
|
}
|
|
|
|
/* Check if the TX buffer is full */
|
|
if ((priv->tx_head - priv->tx_tail) == priv->tx_max)
|
|
netif_stop_queue(ndev);
|
|
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
/**
|
|
* xcan_rx - Is called from CAN isr to complete the received
|
|
* frame processing
|
|
* @ndev: Pointer to net_device structure
|
|
*
|
|
* This function is invoked from the CAN isr(poll) to process the Rx frames. It
|
|
* does minimal processing and invokes "netif_receive_skb" to complete further
|
|
* processing.
|
|
* Return: 1 on success and 0 on failure.
|
|
*/
|
|
static int xcan_rx(struct net_device *ndev)
|
|
{
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
struct net_device_stats *stats = &ndev->stats;
|
|
struct can_frame *cf;
|
|
struct sk_buff *skb;
|
|
u32 id_xcan, dlc, data[2] = {0, 0};
|
|
|
|
skb = alloc_can_skb(ndev, &cf);
|
|
if (unlikely(!skb)) {
|
|
stats->rx_dropped++;
|
|
return 0;
|
|
}
|
|
|
|
/* Read a frame from Xilinx zynq CANPS */
|
|
id_xcan = priv->read_reg(priv, XCAN_RXFIFO_ID_OFFSET);
|
|
dlc = priv->read_reg(priv, XCAN_RXFIFO_DLC_OFFSET) >>
|
|
XCAN_DLCR_DLC_SHIFT;
|
|
|
|
/* Change Xilinx CAN data length format to socketCAN data format */
|
|
cf->can_dlc = get_can_dlc(dlc);
|
|
|
|
/* Change Xilinx CAN ID format to socketCAN ID format */
|
|
if (id_xcan & XCAN_IDR_IDE_MASK) {
|
|
/* The received frame is an Extended format frame */
|
|
cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3;
|
|
cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >>
|
|
XCAN_IDR_ID2_SHIFT;
|
|
cf->can_id |= CAN_EFF_FLAG;
|
|
if (id_xcan & XCAN_IDR_RTR_MASK)
|
|
cf->can_id |= CAN_RTR_FLAG;
|
|
} else {
|
|
/* The received frame is a standard format frame */
|
|
cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >>
|
|
XCAN_IDR_ID1_SHIFT;
|
|
if (id_xcan & XCAN_IDR_SRR_MASK)
|
|
cf->can_id |= CAN_RTR_FLAG;
|
|
}
|
|
|
|
if (!(id_xcan & XCAN_IDR_SRR_MASK)) {
|
|
data[0] = priv->read_reg(priv, XCAN_RXFIFO_DW1_OFFSET);
|
|
data[1] = priv->read_reg(priv, XCAN_RXFIFO_DW2_OFFSET);
|
|
|
|
/* Change Xilinx CAN data format to socketCAN data format */
|
|
if (cf->can_dlc > 0)
|
|
*(__be32 *)(cf->data) = cpu_to_be32(data[0]);
|
|
if (cf->can_dlc > 4)
|
|
*(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]);
|
|
}
|
|
|
|
stats->rx_bytes += cf->can_dlc;
|
|
stats->rx_packets++;
|
|
netif_receive_skb(skb);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* xcan_err_interrupt - error frame Isr
|
|
* @ndev: net_device pointer
|
|
* @isr: interrupt status register value
|
|
*
|
|
* This is the CAN error interrupt and it will
|
|
* check the the type of error and forward the error
|
|
* frame to upper layers.
|
|
*/
|
|
static void xcan_err_interrupt(struct net_device *ndev, u32 isr)
|
|
{
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
struct net_device_stats *stats = &ndev->stats;
|
|
struct can_frame *cf;
|
|
struct sk_buff *skb;
|
|
u32 err_status, status, txerr = 0, rxerr = 0;
|
|
|
|
skb = alloc_can_err_skb(ndev, &cf);
|
|
|
|
err_status = priv->read_reg(priv, XCAN_ESR_OFFSET);
|
|
priv->write_reg(priv, XCAN_ESR_OFFSET, err_status);
|
|
txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
|
|
rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
|
|
XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
|
|
status = priv->read_reg(priv, XCAN_SR_OFFSET);
|
|
|
|
if (isr & XCAN_IXR_BSOFF_MASK) {
|
|
priv->can.state = CAN_STATE_BUS_OFF;
|
|
priv->can.can_stats.bus_off++;
|
|
/* Leave device in Config Mode in bus-off state */
|
|
priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
|
|
can_bus_off(ndev);
|
|
if (skb)
|
|
cf->can_id |= CAN_ERR_BUSOFF;
|
|
} else if ((status & XCAN_SR_ESTAT_MASK) == XCAN_SR_ESTAT_MASK) {
|
|
priv->can.state = CAN_STATE_ERROR_PASSIVE;
|
|
priv->can.can_stats.error_passive++;
|
|
if (skb) {
|
|
cf->can_id |= CAN_ERR_CRTL;
|
|
cf->data[1] = (rxerr > 127) ?
|
|
CAN_ERR_CRTL_RX_PASSIVE :
|
|
CAN_ERR_CRTL_TX_PASSIVE;
|
|
cf->data[6] = txerr;
|
|
cf->data[7] = rxerr;
|
|
}
|
|
} else if (status & XCAN_SR_ERRWRN_MASK) {
|
|
priv->can.state = CAN_STATE_ERROR_WARNING;
|
|
priv->can.can_stats.error_warning++;
|
|
if (skb) {
|
|
cf->can_id |= CAN_ERR_CRTL;
|
|
cf->data[1] |= (txerr > rxerr) ?
|
|
CAN_ERR_CRTL_TX_WARNING :
|
|
CAN_ERR_CRTL_RX_WARNING;
|
|
cf->data[6] = txerr;
|
|
cf->data[7] = rxerr;
|
|
}
|
|
}
|
|
|
|
/* Check for Arbitration lost interrupt */
|
|
if (isr & XCAN_IXR_ARBLST_MASK) {
|
|
priv->can.can_stats.arbitration_lost++;
|
|
if (skb) {
|
|
cf->can_id |= CAN_ERR_LOSTARB;
|
|
cf->data[0] = CAN_ERR_LOSTARB_UNSPEC;
|
|
}
|
|
}
|
|
|
|
/* Check for RX FIFO Overflow interrupt */
|
|
if (isr & XCAN_IXR_RXOFLW_MASK) {
|
|
stats->rx_over_errors++;
|
|
stats->rx_errors++;
|
|
priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
|
|
if (skb) {
|
|
cf->can_id |= CAN_ERR_CRTL;
|
|
cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
|
|
}
|
|
}
|
|
|
|
/* Check for error interrupt */
|
|
if (isr & XCAN_IXR_ERROR_MASK) {
|
|
if (skb) {
|
|
cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
|
|
cf->data[2] |= CAN_ERR_PROT_UNSPEC;
|
|
}
|
|
|
|
/* Check for Ack error interrupt */
|
|
if (err_status & XCAN_ESR_ACKER_MASK) {
|
|
stats->tx_errors++;
|
|
if (skb) {
|
|
cf->can_id |= CAN_ERR_ACK;
|
|
cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
|
|
}
|
|
}
|
|
|
|
/* Check for Bit error interrupt */
|
|
if (err_status & XCAN_ESR_BERR_MASK) {
|
|
stats->tx_errors++;
|
|
if (skb) {
|
|
cf->can_id |= CAN_ERR_PROT;
|
|
cf->data[2] = CAN_ERR_PROT_BIT;
|
|
}
|
|
}
|
|
|
|
/* Check for Stuff error interrupt */
|
|
if (err_status & XCAN_ESR_STER_MASK) {
|
|
stats->rx_errors++;
|
|
if (skb) {
|
|
cf->can_id |= CAN_ERR_PROT;
|
|
cf->data[2] = CAN_ERR_PROT_STUFF;
|
|
}
|
|
}
|
|
|
|
/* Check for Form error interrupt */
|
|
if (err_status & XCAN_ESR_FMER_MASK) {
|
|
stats->rx_errors++;
|
|
if (skb) {
|
|
cf->can_id |= CAN_ERR_PROT;
|
|
cf->data[2] = CAN_ERR_PROT_FORM;
|
|
}
|
|
}
|
|
|
|
/* Check for CRC error interrupt */
|
|
if (err_status & XCAN_ESR_CRCER_MASK) {
|
|
stats->rx_errors++;
|
|
if (skb) {
|
|
cf->can_id |= CAN_ERR_PROT;
|
|
cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ |
|
|
CAN_ERR_PROT_LOC_CRC_DEL;
|
|
}
|
|
}
|
|
priv->can.can_stats.bus_error++;
|
|
}
|
|
|
|
if (skb) {
|
|
stats->rx_packets++;
|
|
stats->rx_bytes += cf->can_dlc;
|
|
netif_rx(skb);
|
|
}
|
|
|
|
netdev_dbg(ndev, "%s: error status register:0x%x\n",
|
|
__func__, priv->read_reg(priv, XCAN_ESR_OFFSET));
|
|
}
|
|
|
|
/**
|
|
* xcan_state_interrupt - It will check the state of the CAN device
|
|
* @ndev: net_device pointer
|
|
* @isr: interrupt status register value
|
|
*
|
|
* This will checks the state of the CAN device
|
|
* and puts the device into appropriate state.
|
|
*/
|
|
static void xcan_state_interrupt(struct net_device *ndev, u32 isr)
|
|
{
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
|
|
/* Check for Sleep interrupt if set put CAN device in sleep state */
|
|
if (isr & XCAN_IXR_SLP_MASK)
|
|
priv->can.state = CAN_STATE_SLEEPING;
|
|
|
|
/* Check for Wake up interrupt if set put CAN device in Active state */
|
|
if (isr & XCAN_IXR_WKUP_MASK)
|
|
priv->can.state = CAN_STATE_ERROR_ACTIVE;
|
|
}
|
|
|
|
/**
|
|
* xcan_rx_poll - Poll routine for rx packets (NAPI)
|
|
* @napi: napi structure pointer
|
|
* @quota: Max number of rx packets to be processed.
|
|
*
|
|
* This is the poll routine for rx part.
|
|
* It will process the packets maximux quota value.
|
|
*
|
|
* Return: number of packets received
|
|
*/
|
|
static int xcan_rx_poll(struct napi_struct *napi, int quota)
|
|
{
|
|
struct net_device *ndev = napi->dev;
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
u32 isr, ier;
|
|
int work_done = 0;
|
|
|
|
isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
|
|
while ((isr & XCAN_IXR_RXNEMP_MASK) && (work_done < quota)) {
|
|
if (isr & XCAN_IXR_RXOK_MASK) {
|
|
priv->write_reg(priv, XCAN_ICR_OFFSET,
|
|
XCAN_IXR_RXOK_MASK);
|
|
work_done += xcan_rx(ndev);
|
|
} else {
|
|
priv->write_reg(priv, XCAN_ICR_OFFSET,
|
|
XCAN_IXR_RXNEMP_MASK);
|
|
break;
|
|
}
|
|
priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXNEMP_MASK);
|
|
isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
|
|
}
|
|
|
|
if (work_done)
|
|
can_led_event(ndev, CAN_LED_EVENT_RX);
|
|
|
|
if (work_done < quota) {
|
|
napi_complete(napi);
|
|
ier = priv->read_reg(priv, XCAN_IER_OFFSET);
|
|
ier |= (XCAN_IXR_RXOK_MASK | XCAN_IXR_RXNEMP_MASK);
|
|
priv->write_reg(priv, XCAN_IER_OFFSET, ier);
|
|
}
|
|
return work_done;
|
|
}
|
|
|
|
/**
|
|
* xcan_tx_interrupt - Tx Done Isr
|
|
* @ndev: net_device pointer
|
|
* @isr: Interrupt status register value
|
|
*/
|
|
static void xcan_tx_interrupt(struct net_device *ndev, u32 isr)
|
|
{
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
struct net_device_stats *stats = &ndev->stats;
|
|
|
|
while ((priv->tx_head - priv->tx_tail > 0) &&
|
|
(isr & XCAN_IXR_TXOK_MASK)) {
|
|
priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK);
|
|
can_get_echo_skb(ndev, priv->tx_tail %
|
|
priv->tx_max);
|
|
priv->tx_tail++;
|
|
stats->tx_packets++;
|
|
isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
|
|
}
|
|
can_led_event(ndev, CAN_LED_EVENT_TX);
|
|
netif_wake_queue(ndev);
|
|
}
|
|
|
|
/**
|
|
* xcan_interrupt - CAN Isr
|
|
* @irq: irq number
|
|
* @dev_id: device id poniter
|
|
*
|
|
* This is the xilinx CAN Isr. It checks for the type of interrupt
|
|
* and invokes the corresponding ISR.
|
|
*
|
|
* Return:
|
|
* IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
|
|
*/
|
|
static irqreturn_t xcan_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct net_device *ndev = (struct net_device *)dev_id;
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
u32 isr, ier;
|
|
|
|
/* Get the interrupt status from Xilinx CAN */
|
|
isr = priv->read_reg(priv, XCAN_ISR_OFFSET);
|
|
if (!isr)
|
|
return IRQ_NONE;
|
|
|
|
/* Check for the type of interrupt and Processing it */
|
|
if (isr & (XCAN_IXR_SLP_MASK | XCAN_IXR_WKUP_MASK)) {
|
|
priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK |
|
|
XCAN_IXR_WKUP_MASK));
|
|
xcan_state_interrupt(ndev, isr);
|
|
}
|
|
|
|
/* Check for Tx interrupt and Processing it */
|
|
if (isr & XCAN_IXR_TXOK_MASK)
|
|
xcan_tx_interrupt(ndev, isr);
|
|
|
|
/* Check for the type of error interrupt and Processing it */
|
|
if (isr & (XCAN_IXR_ERROR_MASK | XCAN_IXR_RXOFLW_MASK |
|
|
XCAN_IXR_BSOFF_MASK | XCAN_IXR_ARBLST_MASK)) {
|
|
priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_ERROR_MASK |
|
|
XCAN_IXR_RXOFLW_MASK | XCAN_IXR_BSOFF_MASK |
|
|
XCAN_IXR_ARBLST_MASK));
|
|
xcan_err_interrupt(ndev, isr);
|
|
}
|
|
|
|
/* Check for the type of receive interrupt and Processing it */
|
|
if (isr & (XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK)) {
|
|
ier = priv->read_reg(priv, XCAN_IER_OFFSET);
|
|
ier &= ~(XCAN_IXR_RXNEMP_MASK | XCAN_IXR_RXOK_MASK);
|
|
priv->write_reg(priv, XCAN_IER_OFFSET, ier);
|
|
napi_schedule(&priv->napi);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/**
|
|
* xcan_chip_stop - Driver stop routine
|
|
* @ndev: Pointer to net_device structure
|
|
*
|
|
* This is the drivers stop routine. It will disable the
|
|
* interrupts and put the device into configuration mode.
|
|
*/
|
|
static void xcan_chip_stop(struct net_device *ndev)
|
|
{
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
u32 ier;
|
|
|
|
/* Disable interrupts and leave the can in configuration mode */
|
|
ier = priv->read_reg(priv, XCAN_IER_OFFSET);
|
|
ier &= ~XCAN_INTR_ALL;
|
|
priv->write_reg(priv, XCAN_IER_OFFSET, ier);
|
|
priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK);
|
|
priv->can.state = CAN_STATE_STOPPED;
|
|
}
|
|
|
|
/**
|
|
* xcan_open - Driver open routine
|
|
* @ndev: Pointer to net_device structure
|
|
*
|
|
* This is the driver open routine.
|
|
* Return: 0 on success and failure value on error
|
|
*/
|
|
static int xcan_open(struct net_device *ndev)
|
|
{
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
int ret;
|
|
|
|
ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags,
|
|
ndev->name, ndev);
|
|
if (ret < 0) {
|
|
netdev_err(ndev, "irq allocation for CAN failed\n");
|
|
goto err;
|
|
}
|
|
|
|
ret = clk_prepare_enable(priv->can_clk);
|
|
if (ret) {
|
|
netdev_err(ndev, "unable to enable device clock\n");
|
|
goto err_irq;
|
|
}
|
|
|
|
ret = clk_prepare_enable(priv->bus_clk);
|
|
if (ret) {
|
|
netdev_err(ndev, "unable to enable bus clock\n");
|
|
goto err_can_clk;
|
|
}
|
|
|
|
/* Set chip into reset mode */
|
|
ret = set_reset_mode(ndev);
|
|
if (ret < 0) {
|
|
netdev_err(ndev, "mode resetting failed!\n");
|
|
goto err_bus_clk;
|
|
}
|
|
|
|
/* Common open */
|
|
ret = open_candev(ndev);
|
|
if (ret)
|
|
goto err_bus_clk;
|
|
|
|
ret = xcan_chip_start(ndev);
|
|
if (ret < 0) {
|
|
netdev_err(ndev, "xcan_chip_start failed!\n");
|
|
goto err_candev;
|
|
}
|
|
|
|
can_led_event(ndev, CAN_LED_EVENT_OPEN);
|
|
napi_enable(&priv->napi);
|
|
netif_start_queue(ndev);
|
|
|
|
return 0;
|
|
|
|
err_candev:
|
|
close_candev(ndev);
|
|
err_bus_clk:
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
err_can_clk:
|
|
clk_disable_unprepare(priv->can_clk);
|
|
err_irq:
|
|
free_irq(ndev->irq, ndev);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* xcan_close - Driver close routine
|
|
* @ndev: Pointer to net_device structure
|
|
*
|
|
* Return: 0 always
|
|
*/
|
|
static int xcan_close(struct net_device *ndev)
|
|
{
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
|
|
netif_stop_queue(ndev);
|
|
napi_disable(&priv->napi);
|
|
xcan_chip_stop(ndev);
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
clk_disable_unprepare(priv->can_clk);
|
|
free_irq(ndev->irq, ndev);
|
|
close_candev(ndev);
|
|
|
|
can_led_event(ndev, CAN_LED_EVENT_STOP);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* xcan_get_berr_counter - error counter routine
|
|
* @ndev: Pointer to net_device structure
|
|
* @bec: Pointer to can_berr_counter structure
|
|
*
|
|
* This is the driver error counter routine.
|
|
* Return: 0 on success and failure value on error
|
|
*/
|
|
static int xcan_get_berr_counter(const struct net_device *ndev,
|
|
struct can_berr_counter *bec)
|
|
{
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(priv->can_clk);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = clk_prepare_enable(priv->bus_clk);
|
|
if (ret)
|
|
goto err_clk;
|
|
|
|
bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK;
|
|
bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) &
|
|
XCAN_ECR_REC_MASK) >> XCAN_ESR_REC_SHIFT);
|
|
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
clk_disable_unprepare(priv->can_clk);
|
|
|
|
return 0;
|
|
|
|
err_clk:
|
|
clk_disable_unprepare(priv->can_clk);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
|
|
static const struct net_device_ops xcan_netdev_ops = {
|
|
.ndo_open = xcan_open,
|
|
.ndo_stop = xcan_close,
|
|
.ndo_start_xmit = xcan_start_xmit,
|
|
};
|
|
|
|
/**
|
|
* xcan_suspend - Suspend method for the driver
|
|
* @dev: Address of the platform_device structure
|
|
*
|
|
* Put the driver into low power mode.
|
|
* Return: 0 always
|
|
*/
|
|
static int __maybe_unused xcan_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = dev_get_drvdata(dev);
|
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
|
|
if (netif_running(ndev)) {
|
|
netif_stop_queue(ndev);
|
|
netif_device_detach(ndev);
|
|
}
|
|
|
|
priv->write_reg(priv, XCAN_MSR_OFFSET, XCAN_MSR_SLEEP_MASK);
|
|
priv->can.state = CAN_STATE_SLEEPING;
|
|
|
|
clk_disable(priv->bus_clk);
|
|
clk_disable(priv->can_clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* xcan_resume - Resume from suspend
|
|
* @dev: Address of the platformdevice structure
|
|
*
|
|
* Resume operation after suspend.
|
|
* Return: 0 on success and failure value on error
|
|
*/
|
|
static int __maybe_unused xcan_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = dev_get_drvdata(dev);
|
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
int ret;
|
|
|
|
ret = clk_enable(priv->bus_clk);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot enable clock.\n");
|
|
return ret;
|
|
}
|
|
ret = clk_enable(priv->can_clk);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot enable clock.\n");
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
return ret;
|
|
}
|
|
|
|
priv->write_reg(priv, XCAN_MSR_OFFSET, 0);
|
|
priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK);
|
|
priv->can.state = CAN_STATE_ERROR_ACTIVE;
|
|
|
|
if (netif_running(ndev)) {
|
|
netif_device_attach(ndev);
|
|
netif_start_queue(ndev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(xcan_dev_pm_ops, xcan_suspend, xcan_resume);
|
|
|
|
/**
|
|
* xcan_probe - Platform registration call
|
|
* @pdev: Handle to the platform device structure
|
|
*
|
|
* This function does all the memory allocation and registration for the CAN
|
|
* device.
|
|
*
|
|
* Return: 0 on success and failure value on error
|
|
*/
|
|
static int xcan_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *res; /* IO mem resources */
|
|
struct net_device *ndev;
|
|
struct xcan_priv *priv;
|
|
void __iomem *addr;
|
|
int ret, rx_max, tx_max;
|
|
|
|
/* Get the virtual base address for the device */
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
addr = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(addr)) {
|
|
ret = PTR_ERR(addr);
|
|
goto err;
|
|
}
|
|
|
|
ret = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", &tx_max);
|
|
if (ret < 0)
|
|
goto err;
|
|
|
|
ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", &rx_max);
|
|
if (ret < 0)
|
|
goto err;
|
|
|
|
/* Create a CAN device instance */
|
|
ndev = alloc_candev(sizeof(struct xcan_priv), tx_max);
|
|
if (!ndev)
|
|
return -ENOMEM;
|
|
|
|
priv = netdev_priv(ndev);
|
|
priv->dev = ndev;
|
|
priv->can.bittiming_const = &xcan_bittiming_const;
|
|
priv->can.do_set_mode = xcan_do_set_mode;
|
|
priv->can.do_get_berr_counter = xcan_get_berr_counter;
|
|
priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
|
|
CAN_CTRLMODE_BERR_REPORTING;
|
|
priv->reg_base = addr;
|
|
priv->tx_max = tx_max;
|
|
|
|
/* Get IRQ for the device */
|
|
ndev->irq = platform_get_irq(pdev, 0);
|
|
ndev->flags |= IFF_ECHO; /* We support local echo */
|
|
|
|
platform_set_drvdata(pdev, ndev);
|
|
SET_NETDEV_DEV(ndev, &pdev->dev);
|
|
ndev->netdev_ops = &xcan_netdev_ops;
|
|
|
|
/* Getting the CAN can_clk info */
|
|
priv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
|
|
if (IS_ERR(priv->can_clk)) {
|
|
dev_err(&pdev->dev, "Device clock not found.\n");
|
|
ret = PTR_ERR(priv->can_clk);
|
|
goto err_free;
|
|
}
|
|
/* Check for type of CAN device */
|
|
if (of_device_is_compatible(pdev->dev.of_node,
|
|
"xlnx,zynq-can-1.0")) {
|
|
priv->bus_clk = devm_clk_get(&pdev->dev, "pclk");
|
|
if (IS_ERR(priv->bus_clk)) {
|
|
dev_err(&pdev->dev, "bus clock not found\n");
|
|
ret = PTR_ERR(priv->bus_clk);
|
|
goto err_free;
|
|
}
|
|
} else {
|
|
priv->bus_clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
|
|
if (IS_ERR(priv->bus_clk)) {
|
|
dev_err(&pdev->dev, "bus clock not found\n");
|
|
ret = PTR_ERR(priv->bus_clk);
|
|
goto err_free;
|
|
}
|
|
}
|
|
|
|
ret = clk_prepare_enable(priv->can_clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to enable device clock\n");
|
|
goto err_free;
|
|
}
|
|
|
|
ret = clk_prepare_enable(priv->bus_clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "unable to enable bus clock\n");
|
|
goto err_unprepare_disable_dev;
|
|
}
|
|
|
|
priv->write_reg = xcan_write_reg_le;
|
|
priv->read_reg = xcan_read_reg_le;
|
|
|
|
if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) {
|
|
priv->write_reg = xcan_write_reg_be;
|
|
priv->read_reg = xcan_read_reg_be;
|
|
}
|
|
|
|
priv->can.clock.freq = clk_get_rate(priv->can_clk);
|
|
|
|
netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max);
|
|
|
|
ret = register_candev(ndev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret);
|
|
goto err_unprepare_disable_busclk;
|
|
}
|
|
|
|
devm_can_led_init(ndev);
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
clk_disable_unprepare(priv->can_clk);
|
|
netdev_dbg(ndev, "reg_base=0x%p irq=%d clock=%d, tx fifo depth:%d\n",
|
|
priv->reg_base, ndev->irq, priv->can.clock.freq,
|
|
priv->tx_max);
|
|
|
|
return 0;
|
|
|
|
err_unprepare_disable_busclk:
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
err_unprepare_disable_dev:
|
|
clk_disable_unprepare(priv->can_clk);
|
|
err_free:
|
|
free_candev(ndev);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* xcan_remove - Unregister the device after releasing the resources
|
|
* @pdev: Handle to the platform device structure
|
|
*
|
|
* This function frees all the resources allocated to the device.
|
|
* Return: 0 always
|
|
*/
|
|
static int xcan_remove(struct platform_device *pdev)
|
|
{
|
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
struct xcan_priv *priv = netdev_priv(ndev);
|
|
|
|
if (set_reset_mode(ndev) < 0)
|
|
netdev_err(ndev, "mode resetting failed!\n");
|
|
|
|
unregister_candev(ndev);
|
|
netif_napi_del(&priv->napi);
|
|
free_candev(ndev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Match table for OF platform binding */
|
|
static struct of_device_id xcan_of_match[] = {
|
|
{ .compatible = "xlnx,zynq-can-1.0", },
|
|
{ .compatible = "xlnx,axi-can-1.00.a", },
|
|
{ /* end of list */ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, xcan_of_match);
|
|
|
|
static struct platform_driver xcan_driver = {
|
|
.probe = xcan_probe,
|
|
.remove = xcan_remove,
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = DRIVER_NAME,
|
|
.pm = &xcan_dev_pm_ops,
|
|
.of_match_table = xcan_of_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(xcan_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Xilinx Inc");
|
|
MODULE_DESCRIPTION("Xilinx CAN interface");
|