Xing Zheng 268aebaa24 clk: rockchip: allow varying mux parameters for cpuclk pll-sources ... Thers are only two parent PLLs that APLL and GPLL for core on the previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed GPLL as alternate parent when core is switching freq. Since RK3399 big.LITTLE architecture, we need to select and adapt more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2016-03-27 13:03:33 +02:00
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clk-cpu.c	clk: rockchip: allow varying mux parameters for cpuclk pll-sources	2016-03-27 13:03:33 +02:00
clk-inverter.c	clk: rockchip: don't return NULL when registering inverter fails	2016-02-15 23:35:20 +01:00
clk-mmc-phase.c	clk: rockchip: don't return NULL when registering mmc branch fails	2016-02-15 23:37:27 +01:00
clk-pll.c	clk: rockchip: check grf when waiting pll lock	2016-02-15 22:38:27 +01:00
clk-rk3036.c	clk: rockchip: allow varying mux parameters for cpuclk pll-sources	2016-03-27 13:03:33 +02:00
clk-rk3188.c	clk: rockchip: allow varying mux parameters for cpuclk pll-sources	2016-03-27 13:03:33 +02:00
clk-rk3228.c	clk: rockchip: allow varying mux parameters for cpuclk pll-sources	2016-03-27 13:03:33 +02:00
clk-rk3288.c	clk: rockchip: allow varying mux parameters for cpuclk pll-sources	2016-03-27 13:03:33 +02:00
clk-rk3368.c	clk: rockchip: allow varying mux parameters for cpuclk pll-sources	2016-03-27 13:03:33 +02:00
clk-rockchip.c
clk.c	Introduction of a factor type and a variant containing a gate	2016-02-15 11:59:45 -08:00
clk.h	clk: rockchip: allow varying mux parameters for cpuclk pll-sources	2016-03-27 13:03:33 +02:00
Makefile	clk: rockchip: add clock controller for rk3228	2015-12-12 20:04:54 +01:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00