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609cc5e1a8
As part of the effort to improve the MediaTek clk drivers, the next step
is to switch from the old 'struct clk' clk prodivder APIs to the new
'struct clk_hw' ones.
Instead of adding new APIs to the MediaTek clk driver library mirroring
the existing ones, moving all drivers to the new APIs, and then removing
the old ones, just migrate everything at the same time. This involves
replacing 'struct clk' with 'struct clk_hw', and 'struct clk_onecell_data'
with 'struct clk_hw_onecell_data', and fixing up all usages.
For now, the clk_register() and co. usage is retained, with __clk_get_hw()
and (struct clk_hw *)->clk used to bridge the difference between the APIs.
These will be replaced in subsequent patches.
Fix up mtk_{alloc,free}_clk_data to use 'struct clk_hw' by hand. Fix up
all other affected call sites with the following coccinelle script.
// Replace type
@@
@@
- struct clk_onecell_data
+ struct clk_hw_onecell_data
// Replace of_clk_add_provider() & of_clk_src_simple_get()
@@
expression NP, DATA;
symbol of_clk_src_onecell_get;
@@
- of_clk_add_provider(
+ of_clk_add_hw_provider(
NP,
- of_clk_src_onecell_get,
+ of_clk_hw_onecell_get,
DATA
)
// Fix register/unregister
@@
identifier CD;
expression E;
identifier fn =~ "unregister";
@@
fn(...,
- CD->clks[E]
+ CD->hws[E]->clk
,...
);
// Fix calls to clk_prepare_enable()
@@
identifier CD;
expression E;
@@
clk_prepare_enable(
- CD->clks[E]
+ CD->hws[E]->clk
);
// Fix pointer assignment
@@
identifier CD;
identifier CLK;
expression E;
@@
- CD->clks[E]
+ CD->hws[E]
=
(
- CLK
+ __clk_get_hw(CLK)
|
ERR_PTR(...)
)
;
// Fix pointer usage
@@
identifier CD;
expression E;
@@
- CD->clks[E]
+ CD->hws[E]
// Fix mtk_clk_pll_get_base()
@@
symbol clk, hw, data;
@@
mtk_clk_pll_get_base(
- struct clk *clk,
+ struct clk_hw *hw,
const struct mtk_pll_data *data
) {
- struct clk_hw *hw = __clk_get_hw(clk);
...
}
// Fix mtk_clk_pll_get_base() usage
@@
identifier CD;
expression E;
@@
mtk_clk_pll_get_base(
- CD->clks[E]
+ CD->hws[E]->clk
,...
);
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220519071610.423372-4-wenst@chromium.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
57 lines
1.2 KiB
C
57 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#ifndef __DRV_CLK_MTK_PLL_H
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#define __DRV_CLK_MTK_PLL_H
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#include <linux/types.h>
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struct clk_ops;
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struct clk_hw_onecell_data;
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struct device_node;
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struct mtk_pll_div_table {
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u32 div;
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unsigned long freq;
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};
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#define HAVE_RST_BAR BIT(0)
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#define PLL_AO BIT(1)
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struct mtk_pll_data {
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int id;
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const char *name;
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u32 reg;
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u32 pwr_reg;
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u32 en_mask;
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u32 pd_reg;
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u32 tuner_reg;
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u32 tuner_en_reg;
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u8 tuner_en_bit;
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int pd_shift;
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unsigned int flags;
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const struct clk_ops *ops;
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u32 rst_bar_mask;
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unsigned long fmin;
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unsigned long fmax;
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int pcwbits;
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int pcwibits;
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u32 pcw_reg;
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int pcw_shift;
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u32 pcw_chg_reg;
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const struct mtk_pll_div_table *div_table;
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const char *parent_name;
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u32 en_reg;
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u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
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};
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int mtk_clk_register_plls(struct device_node *node,
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const struct mtk_pll_data *plls, int num_plls,
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struct clk_hw_onecell_data *clk_data);
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void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
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struct clk_hw_onecell_data *clk_data);
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#endif /* __DRV_CLK_MTK_PLL_H */
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