linux-stable/arch/riscv
Alan Kao bc03109582 riscv: fix accessing 8-byte variable from RV32
[ Upstream commit dbee9c9c45 ]

A memory save operation to 8-byte variable in RV32 is divided into
two sw instructions in the put_user macro.  The current fixup returns
execution flow to the second sw instead of the one after it.

This patch fixes this fixup code according to the load access part.

Signed-off-by: Alan Kao<alankao@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Cc: Vincent Chen <deanbo422@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-05-08 07:21:47 +02:00
..
configs irqchip: add a SiFive PLIC driver 2018-08-13 08:31:32 -07:00
include riscv: fix accessing 8-byte variable from RV32 2019-05-08 07:21:47 +02:00
kernel riscv: fixup max_low_pfn with PFN_DOWN. 2019-03-13 14:02:27 -07:00
lib RISC-V: implement __lshrti3. 2018-08-13 08:31:30 -07:00
mm riscv: fixup max_low_pfn with PFN_DOWN. 2019-03-13 14:02:27 -07:00
Kconfig kconfig: include kernel/Kconfig.preempt from init/Kconfig 2018-08-02 08:06:54 +09:00
Kconfig.debug Kconfig: consolidate the "Kernel hacking" menu 2018-08-02 08:06:48 +09:00
Makefile riscv: add missing vdso_install target 2018-12-01 09:37:33 +01:00