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![Jim Bride](/assets/img/avatar_default.png)
Add the PLL selection code for HSW/BDW/BXT/SKL into a stand-alone function in order to allow for the implementation of a platform neutral upfront link training function. v4: * Removed dereferencing NULL pointer in case of failure (Dhinakaran Pandiyan) v3: * Add Hooks for all DDI platforms into this standalone function v2: * Change the macro to use dev_priv instead of dev (David Weinehall) Reviewed-by: Durgadoss R <durgadoss.r@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
179 lines
5.5 KiB
C
179 lines
5.5 KiB
C
/*
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* Copyright © 2012-2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_DPLL_MGR_H_
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#define _INTEL_DPLL_MGR_H_
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/*FIXME: Move this to a more appropriate place. */
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#define abs_diff(a, b) ({ \
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typeof(a) __a = (a); \
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typeof(b) __b = (b); \
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(void) (&__a == &__b); \
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__a > __b ? (__a - __b) : (__b - __a); })
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struct drm_i915_private;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_encoder;
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struct intel_shared_dpll;
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struct intel_dpll_mgr;
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enum intel_dpll_id {
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DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
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/* real shared dpll ids must be >= 0 */
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DPLL_ID_PCH_PLL_A = 0,
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DPLL_ID_PCH_PLL_B = 1,
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/* hsw/bdw */
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DPLL_ID_WRPLL1 = 0,
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DPLL_ID_WRPLL2 = 1,
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DPLL_ID_SPLL = 2,
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DPLL_ID_LCPLL_810 = 3,
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DPLL_ID_LCPLL_1350 = 4,
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DPLL_ID_LCPLL_2700 = 5,
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/* skl */
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DPLL_ID_SKL_DPLL0 = 0,
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DPLL_ID_SKL_DPLL1 = 1,
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DPLL_ID_SKL_DPLL2 = 2,
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DPLL_ID_SKL_DPLL3 = 3,
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};
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#define I915_NUM_PLLS 6
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/** Inform the state checker that the DPLL is kept enabled even if not
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* in use by any crtc.
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*/
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#define INTEL_DPLL_ALWAYS_ON (1 << 0)
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struct intel_dpll_hw_state {
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/* i9xx, pch plls */
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uint32_t dpll;
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uint32_t dpll_md;
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uint32_t fp0;
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uint32_t fp1;
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/* hsw, bdw */
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uint32_t wrpll;
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uint32_t spll;
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/* skl */
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/*
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* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
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* lower part of ctrl1 and they get shifted into position when writing
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* the register. This allows us to easily compare the state to share
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* the DPLL.
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*/
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uint32_t ctrl1;
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/* HDMI only, 0 when used for DP */
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uint32_t cfgcr1, cfgcr2;
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/* bxt */
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uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
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pcsdw12;
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};
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struct intel_shared_dpll_config {
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unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
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struct intel_dpll_hw_state hw_state;
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};
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struct intel_shared_dpll_funcs {
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/* The mode_set hook is optional and should be used together with the
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* intel_prepare_shared_dpll function. */
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void (*mode_set)(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll);
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void (*enable)(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll);
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void (*disable)(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll);
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bool (*get_hw_state)(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll,
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struct intel_dpll_hw_state *hw_state);
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};
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struct intel_shared_dpll {
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struct intel_shared_dpll_config config;
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unsigned active_mask; /* mask of active CRTCs (i.e. DPMS on) */
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bool on; /* is the PLL actually active? Disabled during modeset */
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const char *name;
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/* should match the index in the dev_priv->shared_dplls array */
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enum intel_dpll_id id;
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struct intel_shared_dpll_funcs funcs;
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uint32_t flags;
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};
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#define SKL_DPLL0 0
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#define SKL_DPLL1 1
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#define SKL_DPLL2 2
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#define SKL_DPLL3 3
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/* shared dpll functions */
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struct intel_shared_dpll *
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intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
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enum intel_dpll_id id);
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enum intel_dpll_id
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intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll);
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void
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intel_shared_dpll_config_get(struct intel_shared_dpll_config *config,
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struct intel_shared_dpll *pll,
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struct intel_crtc *crtc);
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void
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intel_shared_dpll_config_put(struct intel_shared_dpll_config *config,
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struct intel_shared_dpll *pll,
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struct intel_crtc *crtc);
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void assert_shared_dpll(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll *pll,
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bool state);
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#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
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#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
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struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
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struct intel_crtc_state *state,
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struct intel_encoder *encoder);
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void intel_prepare_shared_dpll(struct intel_crtc *crtc);
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void intel_enable_shared_dpll(struct intel_crtc *crtc);
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void intel_disable_shared_dpll(struct intel_crtc *crtc);
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void intel_shared_dpll_commit(struct drm_atomic_state *state);
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void intel_shared_dpll_init(struct drm_device *dev);
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/* BXT dpll related functions */
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bool bxt_ddi_dp_set_dpll_hw_state(int clock,
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struct intel_dpll_hw_state *dpll_hw_state);
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/* SKL dpll related functions */
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bool skl_ddi_dp_set_dpll_hw_state(int clock,
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struct intel_dpll_hw_state *dpll_hw_state);
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struct intel_shared_dpll *skl_find_link_pll(struct drm_i915_private *dev_priv,
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int clock);
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/* HSW dpll related functions */
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struct intel_shared_dpll *hsw_ddi_dp_get_dpll(struct intel_encoder *encoder,
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int clock);
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#endif /* _INTEL_DPLL_MGR_H_ */
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