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4bf59902b5
The MMC sample and drv clock for rockchip platforms are derived from the bus clock output to the MMC/SDIO card. So it should never happens that the clk rate is zero given it should inherits the clock rate from its parent. If something goes wrong and makes the clock rate to be zero, the calculation would be wrong but may still make the mmc tuning process work luckily. However it makes people harder to debug when the following data transfer is unstable. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
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|---|---|---|
| .. | ||
| clk-cpu.c | ||
| clk-ddr.c | ||
| clk-inverter.c | ||
| clk-mmc-phase.c | ||
| clk-muxgrf.c | ||
| clk-pll.c | ||
| clk-rk3036.c | ||
| clk-rk3128.c | ||
| clk-rk3188.c | ||
| clk-rk3228.c | ||
| clk-rk3288.c | ||
| clk-rk3328.c | ||
| clk-rk3368.c | ||
| clk-rk3399.c | ||
| clk-rockchip.c | ||
| clk-rv1108.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||
| softrst.c | ||