265 lines
8.7 KiB
C
265 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012-2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ARM64_KVM_HYP_SYSREG_SR_H__
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#define __ARM64_KVM_HYP_SYSREG_SR_H__
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#include <linux/compiler.h>
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#include <linux/kvm_host.h>
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#include <asm/kprobes.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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static inline void __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
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{
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ctxt_sys_reg(ctxt, MDSCR_EL1) = read_sysreg(mdscr_el1);
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}
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static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
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{
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ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0);
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ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0);
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}
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static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt)
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{
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struct kvm_vcpu *vcpu = ctxt->__hyp_running_vcpu;
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if (!vcpu)
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vcpu = container_of(ctxt, struct kvm_vcpu, arch.ctxt);
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return vcpu;
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}
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static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt)
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{
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struct kvm_vcpu *vcpu = ctxt_to_vcpu(ctxt);
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return kvm_has_mte(kern_hyp_va(vcpu->kvm));
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}
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static inline bool ctxt_has_s1pie(struct kvm_cpu_context *ctxt)
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{
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struct kvm_vcpu *vcpu;
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if (!cpus_have_final_cap(ARM64_HAS_S1PIE))
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return false;
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vcpu = ctxt_to_vcpu(ctxt);
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return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64MMFR3_EL1, S1PIE, IMP);
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}
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static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
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{
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ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR);
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ctxt_sys_reg(ctxt, CPACR_EL1) = read_sysreg_el1(SYS_CPACR);
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ctxt_sys_reg(ctxt, TTBR0_EL1) = read_sysreg_el1(SYS_TTBR0);
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ctxt_sys_reg(ctxt, TTBR1_EL1) = read_sysreg_el1(SYS_TTBR1);
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ctxt_sys_reg(ctxt, TCR_EL1) = read_sysreg_el1(SYS_TCR);
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if (cpus_have_final_cap(ARM64_HAS_TCR2))
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ctxt_sys_reg(ctxt, TCR2_EL1) = read_sysreg_el1(SYS_TCR2);
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ctxt_sys_reg(ctxt, ESR_EL1) = read_sysreg_el1(SYS_ESR);
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ctxt_sys_reg(ctxt, AFSR0_EL1) = read_sysreg_el1(SYS_AFSR0);
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ctxt_sys_reg(ctxt, AFSR1_EL1) = read_sysreg_el1(SYS_AFSR1);
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ctxt_sys_reg(ctxt, FAR_EL1) = read_sysreg_el1(SYS_FAR);
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ctxt_sys_reg(ctxt, MAIR_EL1) = read_sysreg_el1(SYS_MAIR);
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ctxt_sys_reg(ctxt, VBAR_EL1) = read_sysreg_el1(SYS_VBAR);
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ctxt_sys_reg(ctxt, CONTEXTIDR_EL1) = read_sysreg_el1(SYS_CONTEXTIDR);
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ctxt_sys_reg(ctxt, AMAIR_EL1) = read_sysreg_el1(SYS_AMAIR);
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ctxt_sys_reg(ctxt, CNTKCTL_EL1) = read_sysreg_el1(SYS_CNTKCTL);
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if (ctxt_has_s1pie(ctxt)) {
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ctxt_sys_reg(ctxt, PIR_EL1) = read_sysreg_el1(SYS_PIR);
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ctxt_sys_reg(ctxt, PIRE0_EL1) = read_sysreg_el1(SYS_PIRE0);
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}
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ctxt_sys_reg(ctxt, PAR_EL1) = read_sysreg_par();
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ctxt_sys_reg(ctxt, TPIDR_EL1) = read_sysreg(tpidr_el1);
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if (ctxt_has_mte(ctxt)) {
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ctxt_sys_reg(ctxt, TFSR_EL1) = read_sysreg_el1(SYS_TFSR);
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ctxt_sys_reg(ctxt, TFSRE0_EL1) = read_sysreg_s(SYS_TFSRE0_EL1);
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}
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ctxt_sys_reg(ctxt, SP_EL1) = read_sysreg(sp_el1);
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ctxt_sys_reg(ctxt, ELR_EL1) = read_sysreg_el1(SYS_ELR);
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ctxt_sys_reg(ctxt, SPSR_EL1) = read_sysreg_el1(SYS_SPSR);
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}
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static inline void __sysreg_save_el2_return_state(struct kvm_cpu_context *ctxt)
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{
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ctxt->regs.pc = read_sysreg_el2(SYS_ELR);
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/*
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* Guest PSTATE gets saved at guest fixup time in all
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* cases. We still need to handle the nVHE host side here.
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*/
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if (!has_vhe() && ctxt->__hyp_running_vcpu)
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ctxt->regs.pstate = read_sysreg_el2(SYS_SPSR);
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if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
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ctxt_sys_reg(ctxt, DISR_EL1) = read_sysreg_s(SYS_VDISR_EL2);
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}
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static inline void __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
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{
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write_sysreg(ctxt_sys_reg(ctxt, MDSCR_EL1), mdscr_el1);
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}
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static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
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{
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write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0);
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write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0);
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}
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static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
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{
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write_sysreg(ctxt_sys_reg(ctxt, MPIDR_EL1), vmpidr_el2);
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if (has_vhe() ||
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!cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) {
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write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
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write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
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} else if (!ctxt->__hyp_running_vcpu) {
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/*
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* Must only be done for guest registers, hence the context
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* test. We're coming from the host, so SCTLR.M is already
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* set. Pairs with nVHE's __activate_traps().
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*/
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write_sysreg_el1((ctxt_sys_reg(ctxt, TCR_EL1) |
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TCR_EPD1_MASK | TCR_EPD0_MASK),
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SYS_TCR);
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isb();
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}
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write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1), SYS_CPACR);
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write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1), SYS_TTBR0);
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write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1), SYS_TTBR1);
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if (cpus_have_final_cap(ARM64_HAS_TCR2))
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write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL1), SYS_TCR2);
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write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1), SYS_ESR);
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write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL1), SYS_AFSR0);
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write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL1), SYS_AFSR1);
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write_sysreg_el1(ctxt_sys_reg(ctxt, FAR_EL1), SYS_FAR);
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write_sysreg_el1(ctxt_sys_reg(ctxt, MAIR_EL1), SYS_MAIR);
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write_sysreg_el1(ctxt_sys_reg(ctxt, VBAR_EL1), SYS_VBAR);
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write_sysreg_el1(ctxt_sys_reg(ctxt, CONTEXTIDR_EL1), SYS_CONTEXTIDR);
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write_sysreg_el1(ctxt_sys_reg(ctxt, AMAIR_EL1), SYS_AMAIR);
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write_sysreg_el1(ctxt_sys_reg(ctxt, CNTKCTL_EL1), SYS_CNTKCTL);
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if (ctxt_has_s1pie(ctxt)) {
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write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR);
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write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0);
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}
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write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1), par_el1);
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write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1), tpidr_el1);
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if (ctxt_has_mte(ctxt)) {
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write_sysreg_el1(ctxt_sys_reg(ctxt, TFSR_EL1), SYS_TFSR);
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write_sysreg_s(ctxt_sys_reg(ctxt, TFSRE0_EL1), SYS_TFSRE0_EL1);
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}
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if (!has_vhe() &&
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cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT) &&
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ctxt->__hyp_running_vcpu) {
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/*
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* Must only be done for host registers, hence the context
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* test. Pairs with nVHE's __deactivate_traps().
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*/
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isb();
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/*
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* At this stage, and thanks to the above isb(), S2 is
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* deconfigured and disabled. We can now restore the host's
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* S1 configuration: SCTLR, and only then TCR.
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*/
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write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR);
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isb();
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write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR);
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}
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write_sysreg(ctxt_sys_reg(ctxt, SP_EL1), sp_el1);
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write_sysreg_el1(ctxt_sys_reg(ctxt, ELR_EL1), SYS_ELR);
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write_sysreg_el1(ctxt_sys_reg(ctxt, SPSR_EL1), SYS_SPSR);
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}
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/* Read the VCPU state's PSTATE, but translate (v)EL2 to EL1. */
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static inline u64 to_hw_pstate(const struct kvm_cpu_context *ctxt)
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{
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u64 mode = ctxt->regs.pstate & (PSR_MODE_MASK | PSR_MODE32_BIT);
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switch (mode) {
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case PSR_MODE_EL2t:
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mode = PSR_MODE_EL1t;
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break;
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case PSR_MODE_EL2h:
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mode = PSR_MODE_EL1h;
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break;
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}
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return (ctxt->regs.pstate & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode;
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}
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static inline void __sysreg_restore_el2_return_state(struct kvm_cpu_context *ctxt)
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{
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u64 pstate = to_hw_pstate(ctxt);
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u64 mode = pstate & PSR_AA32_MODE_MASK;
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/*
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* Safety check to ensure we're setting the CPU up to enter the guest
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* in a less privileged mode.
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*
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* If we are attempting a return to EL2 or higher in AArch64 state,
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* program SPSR_EL2 with M=EL2h and the IL bit set which ensures that
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* we'll take an illegal exception state exception immediately after
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* the ERET to the guest. Attempts to return to AArch32 Hyp will
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* result in an illegal exception return because EL2's execution state
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* is determined by SCR_EL3.RW.
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*/
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if (!(mode & PSR_MODE32_BIT) && mode >= PSR_MODE_EL2t)
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pstate = PSR_MODE_EL2h | PSR_IL_BIT;
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write_sysreg_el2(ctxt->regs.pc, SYS_ELR);
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write_sysreg_el2(pstate, SYS_SPSR);
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if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
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write_sysreg_s(ctxt_sys_reg(ctxt, DISR_EL1), SYS_VDISR_EL2);
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}
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static inline void __sysreg32_save_state(struct kvm_vcpu *vcpu)
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{
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if (!vcpu_el1_is_32bit(vcpu))
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return;
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vcpu->arch.ctxt.spsr_abt = read_sysreg(spsr_abt);
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vcpu->arch.ctxt.spsr_und = read_sysreg(spsr_und);
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vcpu->arch.ctxt.spsr_irq = read_sysreg(spsr_irq);
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vcpu->arch.ctxt.spsr_fiq = read_sysreg(spsr_fiq);
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__vcpu_sys_reg(vcpu, DACR32_EL2) = read_sysreg(dacr32_el2);
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__vcpu_sys_reg(vcpu, IFSR32_EL2) = read_sysreg(ifsr32_el2);
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if (has_vhe() || vcpu_get_flag(vcpu, DEBUG_DIRTY))
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__vcpu_sys_reg(vcpu, DBGVCR32_EL2) = read_sysreg(dbgvcr32_el2);
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}
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static inline void __sysreg32_restore_state(struct kvm_vcpu *vcpu)
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{
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if (!vcpu_el1_is_32bit(vcpu))
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return;
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write_sysreg(vcpu->arch.ctxt.spsr_abt, spsr_abt);
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write_sysreg(vcpu->arch.ctxt.spsr_und, spsr_und);
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write_sysreg(vcpu->arch.ctxt.spsr_irq, spsr_irq);
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write_sysreg(vcpu->arch.ctxt.spsr_fiq, spsr_fiq);
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write_sysreg(__vcpu_sys_reg(vcpu, DACR32_EL2), dacr32_el2);
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write_sysreg(__vcpu_sys_reg(vcpu, IFSR32_EL2), ifsr32_el2);
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if (has_vhe() || vcpu_get_flag(vcpu, DEBUG_DIRTY))
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write_sysreg(__vcpu_sys_reg(vcpu, DBGVCR32_EL2), dbgvcr32_el2);
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}
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#endif /* __ARM64_KVM_HYP_SYSREG_SR_H__ */
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