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![Athira Rajeev](/assets/img/avatar_default.png)
Sampled Instruction Event Register (SIER) field [46:48] identifies the
sampled instruction type. ISA v3.1 says value of 0b111 for this field as
reserved, but in POWER10 it denotes LARX/STCX type which will hopefully
be fixed in ISA v3.1 update.
Patch fixes the functions to handle type value 7 for CPU_FTR_ARCH_31.
Fixes: a64e697cef
("powerpc/perf: power10 Performance Monitoring support")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.ibm.com>
[mpe: Avoid reading mmcra until necessary, use early return to deindent if block]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1614858937-1485-1-git-send-email-atrajeev@linux.vnet.ibm.com
789 lines
20 KiB
C
789 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Common Performance counter support functions for PowerISA v2.07 processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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* Copyright 2013 Michael Ellerman, IBM Corporation.
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* Copyright 2016 Madhavan Srinivasan, IBM Corporation.
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*/
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#include "isa207-common.h"
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PMU_FORMAT_ATTR(event, "config:0-49");
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PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
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PMU_FORMAT_ATTR(mark, "config:8");
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PMU_FORMAT_ATTR(combine, "config:11");
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PMU_FORMAT_ATTR(unit, "config:12-15");
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PMU_FORMAT_ATTR(pmc, "config:16-19");
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PMU_FORMAT_ATTR(cache_sel, "config:20-23");
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PMU_FORMAT_ATTR(sample_mode, "config:24-28");
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PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
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PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
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PMU_FORMAT_ATTR(thresh_start, "config:36-39");
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PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
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static struct attribute *isa207_pmu_format_attr[] = {
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&format_attr_event.attr,
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&format_attr_pmcxsel.attr,
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&format_attr_mark.attr,
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&format_attr_combine.attr,
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&format_attr_unit.attr,
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&format_attr_pmc.attr,
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&format_attr_cache_sel.attr,
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&format_attr_sample_mode.attr,
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&format_attr_thresh_sel.attr,
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&format_attr_thresh_stop.attr,
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&format_attr_thresh_start.attr,
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&format_attr_thresh_cmp.attr,
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NULL,
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};
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struct attribute_group isa207_pmu_format_group = {
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.name = "format",
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.attrs = isa207_pmu_format_attr,
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};
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static inline bool event_is_fab_match(u64 event)
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{
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/* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
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event &= 0xff0fe;
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/* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
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return (event == 0x30056 || event == 0x4f052);
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}
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static bool is_event_valid(u64 event)
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{
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u64 valid_mask = EVENT_VALID_MASK;
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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valid_mask = p10_EVENT_VALID_MASK;
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else if (cpu_has_feature(CPU_FTR_ARCH_300))
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valid_mask = p9_EVENT_VALID_MASK;
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return !(event & ~valid_mask);
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}
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static inline bool is_event_marked(u64 event)
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{
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if (event & EVENT_IS_MARKED)
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return true;
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return false;
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}
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static unsigned long sdar_mod_val(u64 event)
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{
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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return p10_SDAR_MODE(event);
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return p9_SDAR_MODE(event);
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}
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static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
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{
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/*
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* MMCRA[SDAR_MODE] specifices how the SDAR should be updated in
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* continous sampling mode.
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*
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* Incase of Power8:
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* MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling
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* mode and will be un-changed when setting MMCRA[63] (Marked events).
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*
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* Incase of Power9/power10:
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* Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'),
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* or if group already have any marked events.
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* For rest
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* MMCRA[SDAR_MODE] will be set from event code.
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* If sdar_mode from event is zero, default to 0b01. Hardware
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* requires that we set a non-zero value.
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
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*mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
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else if (sdar_mod_val(event))
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*mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT;
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else
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*mmcra |= MMCRA_SDAR_MODE_DCACHE;
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} else
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*mmcra |= MMCRA_SDAR_MODE_TLB;
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}
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static u64 p10_thresh_cmp_val(u64 value)
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{
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int exp = 0;
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u64 result = value;
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if (!value)
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return value;
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/*
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* Incase of P10, thresh_cmp value is not part of raw event code
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* and provided via attr.config1 parameter. To program threshold in MMCRA,
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* take a 18 bit number N and shift right 2 places and increment
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* the exponent E by 1 until the upper 10 bits of N are zero.
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* Write E to the threshold exponent and write the lower 8 bits of N
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* to the threshold mantissa.
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* The max threshold that can be written is 261120.
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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if (value > 261120)
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value = 261120;
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while ((64 - __builtin_clzl(value)) > 8) {
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exp++;
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value >>= 2;
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}
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/*
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* Note that it is invalid to write a mantissa with the
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* upper 2 bits of mantissa being zero, unless the
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* exponent is also zero.
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*/
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if (!(value & 0xC0) && exp)
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result = 0;
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else
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result = (exp << 8) | value;
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}
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return result;
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}
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static u64 thresh_cmp_val(u64 value)
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{
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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value = p10_thresh_cmp_val(value);
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/*
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* Since location of threshold compare bits in MMCRA
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* is different for p8, using different shift value.
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_300))
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return value << p9_MMCRA_THR_CMP_SHIFT;
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else
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return value << MMCRA_THR_CMP_SHIFT;
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}
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static unsigned long combine_from_event(u64 event)
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{
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if (cpu_has_feature(CPU_FTR_ARCH_300))
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return p9_EVENT_COMBINE(event);
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return EVENT_COMBINE(event);
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}
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static unsigned long combine_shift(unsigned long pmc)
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{
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if (cpu_has_feature(CPU_FTR_ARCH_300))
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return p9_MMCR1_COMBINE_SHIFT(pmc);
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return MMCR1_COMBINE_SHIFT(pmc);
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}
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static inline bool event_is_threshold(u64 event)
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{
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return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
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}
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static bool is_thresh_cmp_valid(u64 event)
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{
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unsigned int cmp, exp;
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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return p10_thresh_cmp_val(event) != 0;
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/*
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* Check the mantissa upper two bits are not zero, unless the
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* exponent is also zero. See the THRESH_CMP_MANTISSA doc.
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*/
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cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
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exp = cmp >> 7;
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if (exp && (cmp & 0x60) == 0)
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return false;
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return true;
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}
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static unsigned int dc_ic_rld_quad_l1_sel(u64 event)
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{
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unsigned int cache;
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cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK;
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return cache;
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}
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static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
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{
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u64 ret = PERF_MEM_NA;
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switch(idx) {
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case 0:
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/* Nothing to do */
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break;
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case 1:
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ret = PH(LVL, L1);
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break;
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case 2:
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ret = PH(LVL, L2);
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break;
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case 3:
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ret = PH(LVL, L3);
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break;
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case 4:
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if (sub_idx <= 1)
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ret = PH(LVL, LOC_RAM);
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else if (sub_idx > 1 && sub_idx <= 2)
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ret = PH(LVL, REM_RAM1);
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else
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ret = PH(LVL, REM_RAM2);
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ret |= P(SNOOP, HIT);
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break;
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case 5:
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ret = PH(LVL, REM_CCE1);
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if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
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ret |= P(SNOOP, HIT);
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else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
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ret |= P(SNOOP, HITM);
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break;
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case 6:
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ret = PH(LVL, REM_CCE2);
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if ((sub_idx == 0) || (sub_idx == 2))
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ret |= P(SNOOP, HIT);
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else if ((sub_idx == 1) || (sub_idx == 3))
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ret |= P(SNOOP, HITM);
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break;
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case 7:
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ret = PM(LVL, L1);
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break;
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}
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return ret;
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}
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void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
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struct pt_regs *regs)
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{
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u64 idx;
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u32 sub_idx;
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u64 sier;
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u64 val;
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/* Skip if no SIER support */
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if (!(flags & PPMU_HAS_SIER)) {
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dsrc->val = 0;
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return;
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}
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sier = mfspr(SPRN_SIER);
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val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
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if (val != 1 && val != 2 && !(val == 7 && cpu_has_feature(CPU_FTR_ARCH_31)))
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return;
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idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT;
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sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT;
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dsrc->val = isa207_find_source(idx, sub_idx);
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if (val == 7) {
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u64 mmcra;
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u32 op_type;
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/*
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* Type 0b111 denotes either larx or stcx instruction. Use the
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* MMCRA sampling bits [57:59] along with the type value
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* to determine the exact instruction type. If the sampling
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* criteria is neither load or store, set the type as default
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* to NA.
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*/
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mmcra = mfspr(SPRN_MMCRA);
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op_type = (mmcra >> MMCRA_SAMP_ELIG_SHIFT) & MMCRA_SAMP_ELIG_MASK;
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switch (op_type) {
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case 5:
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dsrc->val |= P(OP, LOAD);
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break;
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case 7:
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dsrc->val |= P(OP, STORE);
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break;
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default:
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dsrc->val |= P(OP, NA);
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break;
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}
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} else {
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dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);
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}
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}
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void isa207_get_mem_weight(u64 *weight, u64 type)
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{
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union perf_sample_weight *weight_fields;
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u64 weight_lat;
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u64 mmcra = mfspr(SPRN_MMCRA);
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u64 exp = MMCRA_THR_CTR_EXP(mmcra);
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u64 mantissa = MMCRA_THR_CTR_MANT(mmcra);
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u64 sier = mfspr(SPRN_SIER);
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u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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mantissa = P10_MMCRA_THR_CTR_MANT(mmcra);
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if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31)))
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weight_lat = 0;
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else
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weight_lat = mantissa << (2 * exp);
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/*
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* Use 64 bit weight field (full) if sample type is
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* WEIGHT.
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*
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* if sample type is WEIGHT_STRUCT:
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* - store memory latency in the lower 32 bits.
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* - For ISA v3.1, use remaining two 16 bit fields of
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* perf_sample_weight to store cycle counter values
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* from sier2.
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*/
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weight_fields = (union perf_sample_weight *)weight;
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if (type & PERF_SAMPLE_WEIGHT)
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weight_fields->full = weight_lat;
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else {
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weight_fields->var1_dw = (u32)weight_lat;
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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weight_fields->var2_w = P10_SIER2_FINISH_CYC(mfspr(SPRN_SIER2));
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weight_fields->var3_w = P10_SIER2_DISPATCH_CYC(mfspr(SPRN_SIER2));
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}
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}
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}
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int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1)
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{
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unsigned int unit, pmc, cache, ebb;
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unsigned long mask, value;
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mask = value = 0;
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if (!is_event_valid(event))
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return -1;
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pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
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unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
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if (cpu_has_feature(CPU_FTR_ARCH_31))
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cache = (event >> EVENT_CACHE_SEL_SHIFT) &
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p10_EVENT_CACHE_SEL_MASK;
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else
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cache = (event >> EVENT_CACHE_SEL_SHIFT) &
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EVENT_CACHE_SEL_MASK;
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ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
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if (pmc) {
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u64 base_event;
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if (pmc > 6)
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return -1;
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/* Ignore Linux defined bits when checking event below */
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base_event = event & ~EVENT_LINUX_MASK;
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if (pmc >= 5 && base_event != 0x500fa &&
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base_event != 0x600f4)
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return -1;
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mask |= CNST_PMC_MASK(pmc);
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value |= CNST_PMC_VAL(pmc);
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/*
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* PMC5 and PMC6 are used to count cycles and instructions and
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* they do not support most of the constraint bits. Add a check
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* to exclude PMC5/6 from most of the constraints except for
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* EBB/BHRB.
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*/
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if (pmc >= 5)
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goto ebb_bhrb;
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}
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if (pmc <= 4) {
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/*
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* Add to number of counters in use. Note this includes events with
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* a PMC of 0 - they still need a PMC, it's just assigned later.
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* Don't count events on PMC 5 & 6, there is only one valid event
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* on each of those counters, and they are handled above.
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*/
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mask |= CNST_NC_MASK;
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value |= CNST_NC_VAL;
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}
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if (unit >= 6 && unit <= 9) {
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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if (unit == 6) {
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mask |= CNST_L2L3_GROUP_MASK;
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value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
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}
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} else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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mask |= CNST_CACHE_GROUP_MASK;
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value |= CNST_CACHE_GROUP_VAL(event & 0xff);
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mask |= CNST_CACHE_PMC4_MASK;
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if (pmc == 4)
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value |= CNST_CACHE_PMC4_VAL;
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} else if (cache & 0x7) {
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/*
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* L2/L3 events contain a cache selector field, which is
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* supposed to be programmed into MMCRC. However MMCRC is only
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* HV writable, and there is no API for guest kernels to modify
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* it. The solution is for the hypervisor to initialise the
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* field to zeroes, and for us to only ever allow events that
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* have a cache selector of zero. The bank selector (bit 3) is
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* irrelevant, as long as the rest of the value is 0.
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*/
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return -1;
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}
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|
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} else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) {
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mask |= CNST_L1_QUAL_MASK;
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value |= CNST_L1_QUAL_VAL(cache);
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}
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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mask |= CNST_RADIX_SCOPE_GROUP_MASK;
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value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT);
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}
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|
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if (is_event_marked(event)) {
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mask |= CNST_SAMPLE_MASK;
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value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
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}
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if (cpu_has_feature(CPU_FTR_ARCH_31)) {
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if (event_is_threshold(event) && is_thresh_cmp_valid(event_config1)) {
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mask |= CNST_THRESH_CTL_SEL_MASK;
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value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT);
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mask |= p10_CNST_THRESH_CMP_MASK;
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value |= p10_CNST_THRESH_CMP_VAL(p10_thresh_cmp_val(event_config1));
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}
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} else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
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mask |= CNST_THRESH_MASK;
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value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
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}
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} else {
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/*
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* Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
|
|
* the threshold control bits are used for the match value.
|
|
*/
|
|
if (event_is_fab_match(event)) {
|
|
mask |= CNST_FAB_MATCH_MASK;
|
|
value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
|
|
} else {
|
|
if (!is_thresh_cmp_valid(event))
|
|
return -1;
|
|
|
|
mask |= CNST_THRESH_MASK;
|
|
value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
|
|
}
|
|
}
|
|
|
|
ebb_bhrb:
|
|
if (!pmc && ebb)
|
|
/* EBB events must specify the PMC */
|
|
return -1;
|
|
|
|
if (event & EVENT_WANTS_BHRB) {
|
|
if (!ebb)
|
|
/* Only EBB events can request BHRB */
|
|
return -1;
|
|
|
|
mask |= CNST_IFM_MASK;
|
|
value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
|
|
}
|
|
|
|
/*
|
|
* All events must agree on EBB, either all request it or none.
|
|
* EBB events are pinned & exclusive, so this should never actually
|
|
* hit, but we leave it as a fallback in case.
|
|
*/
|
|
mask |= CNST_EBB_MASK;
|
|
value |= CNST_EBB_VAL(ebb);
|
|
|
|
*maskp = mask;
|
|
*valp = value;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int isa207_compute_mmcr(u64 event[], int n_ev,
|
|
unsigned int hwc[], struct mmcr_regs *mmcr,
|
|
struct perf_event *pevents[], u32 flags)
|
|
{
|
|
unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
|
|
unsigned long mmcr3;
|
|
unsigned int pmc, pmc_inuse;
|
|
int i;
|
|
|
|
pmc_inuse = 0;
|
|
|
|
/* First pass to count resource use */
|
|
for (i = 0; i < n_ev; ++i) {
|
|
pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
|
|
if (pmc)
|
|
pmc_inuse |= 1 << pmc;
|
|
}
|
|
|
|
mmcra = mmcr1 = mmcr2 = mmcr3 = 0;
|
|
|
|
/*
|
|
* Disable bhrb unless explicitly requested
|
|
* by setting MMCRA (BHRBRD) bit.
|
|
*/
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31))
|
|
mmcra |= MMCRA_BHRB_DISABLE;
|
|
|
|
/* Second pass: assign PMCs, set all MMCR1 fields */
|
|
for (i = 0; i < n_ev; ++i) {
|
|
pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
|
|
unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
|
|
combine = combine_from_event(event[i]);
|
|
psel = event[i] & EVENT_PSEL_MASK;
|
|
|
|
if (!pmc) {
|
|
for (pmc = 1; pmc <= 4; ++pmc) {
|
|
if (!(pmc_inuse & (1 << pmc)))
|
|
break;
|
|
}
|
|
|
|
pmc_inuse |= 1 << pmc;
|
|
}
|
|
|
|
if (pmc <= 4) {
|
|
mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
|
|
mmcr1 |= combine << combine_shift(pmc);
|
|
mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
|
|
}
|
|
|
|
/* In continuous sampling mode, update SDAR on TLB miss */
|
|
mmcra_sdar_mode(event[i], &mmcra);
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_300)) {
|
|
cache = dc_ic_rld_quad_l1_sel(event[i]);
|
|
mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
|
|
} else {
|
|
if (event[i] & EVENT_IS_L1) {
|
|
cache = dc_ic_rld_quad_l1_sel(event[i]);
|
|
mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
|
|
}
|
|
}
|
|
|
|
/* Set RADIX_SCOPE_QUAL bit */
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) &
|
|
p10_EVENT_RADIX_SCOPE_QUAL_MASK;
|
|
mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT;
|
|
}
|
|
|
|
if (is_event_marked(event[i])) {
|
|
mmcra |= MMCRA_SAMPLE_ENABLE;
|
|
|
|
val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
|
|
if (val) {
|
|
mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
|
|
mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
|
|
* the threshold bits are used for the match value.
|
|
*/
|
|
if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) {
|
|
mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
|
|
EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
|
|
} else {
|
|
val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
|
|
mmcra |= val << MMCRA_THR_CTL_SHIFT;
|
|
val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
|
|
mmcra |= val << MMCRA_THR_SEL_SHIFT;
|
|
if (!cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
val = (event[i] >> EVENT_THR_CMP_SHIFT) &
|
|
EVENT_THR_CMP_MASK;
|
|
mmcra |= thresh_cmp_val(val);
|
|
} else if (flags & PPMU_HAS_ATTR_CONFIG1) {
|
|
val = (pevents[i]->attr.config1 >> p10_EVENT_THR_CMP_SHIFT) &
|
|
p10_EVENT_THR_CMP_MASK;
|
|
mmcra |= thresh_cmp_val(val);
|
|
}
|
|
}
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) {
|
|
val = (event[i] >> p10_L2L3_EVENT_SHIFT) &
|
|
p10_EVENT_L2L3_SEL_MASK;
|
|
mmcr2 |= val << p10_L2L3_SEL_SHIFT;
|
|
}
|
|
|
|
if (event[i] & EVENT_WANTS_BHRB) {
|
|
val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
|
|
mmcra |= val << MMCRA_IFM_SHIFT;
|
|
}
|
|
|
|
/* set MMCRA (BHRBRD) to 0 if there is user request for BHRB */
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31) &&
|
|
(has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB)))
|
|
mmcra &= ~MMCRA_BHRB_DISABLE;
|
|
|
|
if (pevents[i]->attr.exclude_user)
|
|
mmcr2 |= MMCR2_FCP(pmc);
|
|
|
|
if (pevents[i]->attr.exclude_hv)
|
|
mmcr2 |= MMCR2_FCH(pmc);
|
|
|
|
if (pevents[i]->attr.exclude_kernel) {
|
|
if (cpu_has_feature(CPU_FTR_HVMODE))
|
|
mmcr2 |= MMCR2_FCH(pmc);
|
|
else
|
|
mmcr2 |= MMCR2_FCS(pmc);
|
|
}
|
|
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31)) {
|
|
if (pmc <= 4) {
|
|
val = (event[i] >> p10_EVENT_MMCR3_SHIFT) &
|
|
p10_EVENT_MMCR3_MASK;
|
|
mmcr3 |= val << MMCR3_SHIFT(pmc);
|
|
}
|
|
}
|
|
|
|
hwc[i] = pmc - 1;
|
|
}
|
|
|
|
/* Return MMCRx values */
|
|
mmcr->mmcr0 = 0;
|
|
|
|
/* pmc_inuse is 1-based */
|
|
if (pmc_inuse & 2)
|
|
mmcr->mmcr0 = MMCR0_PMC1CE;
|
|
|
|
if (pmc_inuse & 0x7c)
|
|
mmcr->mmcr0 |= MMCR0_PMCjCE;
|
|
|
|
/* If we're not using PMC 5 or 6, freeze them */
|
|
if (!(pmc_inuse & 0x60))
|
|
mmcr->mmcr0 |= MMCR0_FC56;
|
|
|
|
/*
|
|
* Set mmcr0 (PMCCEXT) for p10 which
|
|
* will restrict access to group B registers
|
|
* when MMCR0 PMCC=0b00.
|
|
*/
|
|
if (cpu_has_feature(CPU_FTR_ARCH_31))
|
|
mmcr->mmcr0 |= MMCR0_PMCCEXT;
|
|
|
|
mmcr->mmcr1 = mmcr1;
|
|
mmcr->mmcra = mmcra;
|
|
mmcr->mmcr2 = mmcr2;
|
|
mmcr->mmcr3 = mmcr3;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
|
|
{
|
|
if (pmc <= 3)
|
|
mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
|
|
}
|
|
|
|
static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size)
|
|
{
|
|
int i, j;
|
|
|
|
for (i = 0; i < size; ++i) {
|
|
if (event < ev_alt[i][0])
|
|
break;
|
|
|
|
for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j)
|
|
if (event == ev_alt[i][j])
|
|
return i;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
|
|
const unsigned int ev_alt[][MAX_ALT])
|
|
{
|
|
int i, j, num_alt = 0;
|
|
u64 alt_event;
|
|
|
|
alt[num_alt++] = event;
|
|
i = find_alternative(event, ev_alt, size);
|
|
if (i >= 0) {
|
|
/* Filter out the original event, it's already in alt[0] */
|
|
for (j = 0; j < MAX_ALT; ++j) {
|
|
alt_event = ev_alt[i][j];
|
|
if (alt_event && alt_event != event)
|
|
alt[num_alt++] = alt_event;
|
|
}
|
|
}
|
|
|
|
if (flags & PPMU_ONLY_COUNT_RUN) {
|
|
/*
|
|
* We're only counting in RUN state, so PM_CYC is equivalent to
|
|
* PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
|
|
*/
|
|
j = num_alt;
|
|
for (i = 0; i < num_alt; ++i) {
|
|
switch (alt[i]) {
|
|
case 0x1e: /* PMC_CYC */
|
|
alt[j++] = 0x600f4; /* PM_RUN_CYC */
|
|
break;
|
|
case 0x600f4:
|
|
alt[j++] = 0x1e;
|
|
break;
|
|
case 0x2: /* PM_INST_CMPL */
|
|
alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
|
|
break;
|
|
case 0x500fa:
|
|
alt[j++] = 0x2;
|
|
break;
|
|
}
|
|
}
|
|
num_alt = j;
|
|
}
|
|
|
|
return num_alt;
|
|
}
|
|
|
|
int isa3XX_check_attr_config(struct perf_event *ev)
|
|
{
|
|
u64 val, sample_mode;
|
|
u64 event = ev->attr.config;
|
|
|
|
val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
|
|
sample_mode = val & 0x3;
|
|
|
|
/*
|
|
* MMCRA[61:62] is Random Sampling Mode (SM).
|
|
* value of 0b11 is reserved.
|
|
*/
|
|
if (sample_mode == 0x3)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Check for all reserved value
|
|
* Source: Performance Monitoring Unit User Guide
|
|
*/
|
|
switch (val) {
|
|
case 0x5:
|
|
case 0x9:
|
|
case 0xD:
|
|
case 0x19:
|
|
case 0x1D:
|
|
case 0x1A:
|
|
case 0x1E:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* MMCRA[48:51]/[52:55]) Threshold Start/Stop
|
|
* Events Selection.
|
|
* 0b11110000/0b00001111 is reserved.
|
|
*/
|
|
val = (event >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
|
|
if (((val & 0xF0) == 0xF0) || ((val & 0xF) == 0xF))
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|