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Previously it was unconditionally used on all Sibyte family SOCs. The M3 bug has to be handled in the TLB exception handler which is extremly performance sensitive, so this modification is expected to deliver around 2-3% performance improvment. This is important as required changes to the M3 workaround will make it more costly. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
41 lines
1 KiB
C
41 lines
1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define __ASM_MIPS_MACH_SIBYTE_WAR_H
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#define R4600_V1_INDEX_ICACHEOP_WAR 0
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#define R4600_V1_HIT_CACHEOP_WAR 0
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R5432_CP0_INTERRUPT_WAR 0
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#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
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defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
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#ifndef __ASSEMBLY__
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extern int sb1250_m3_workaround_needed(void);
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#endif
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#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
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#define SIBYTE_1956_WAR 1
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#else
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif
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#define MIPS4K_ICACHE_REFILL_WAR 0
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#define MIPS_CACHE_SYNC_WAR 0
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#define TX49XX_ICACHE_INDEX_INV_WAR 0
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#define RM9000_CDEX_SMP_WAR 0
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#define ICACHE_REFILLS_WORKAROUND_WAR 0
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#define R10000_LLSC_WAR 0
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#define MIPS34K_MISSED_ITLB_WAR 0
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#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
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