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![Biju Das](/assets/img/avatar_default.png)
As per Chapter 6.5.16 of the RZ/N1 Peripheral Manual, The SJA1000 CAN controller does not support Clock Divider Register compared to the reference Philips SJA1000 device. This patch adds a device quirk to handle this difference. Link: https://lore.kernel.org/all/20220710115248.190280-4-biju.das.jz@bp.renesas.com Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
183 lines
5.5 KiB
C
183 lines
5.5 KiB
C
/*
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* sja1000.h - Philips SJA1000 network device driver
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*
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* Copyright (c) 2003 Matthias Brukner, Trajet Gmbh, Rebenring 33,
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* 38106 Braunschweig, GERMANY
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*
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* Copyright (c) 2002-2007 Volkswagen Group Electronic Research
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Volkswagen nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* Alternatively, provided that this notice is retained in full, this
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* software may be distributed under the terms of the GNU General
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* Public License ("GPL") version 2, in which case the provisions of the
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* GPL apply INSTEAD OF those given above.
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*
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* The provided data structures and external interfaces from this code
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* are not restricted to be used by modules with a GPL compatible license.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#ifndef SJA1000_DEV_H
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#define SJA1000_DEV_H
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#include <linux/irqreturn.h>
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#include <linux/can/dev.h>
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#include <linux/can/platform/sja1000.h>
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#define SJA1000_ECHO_SKB_MAX 1 /* the SJA1000 has one TX buffer object */
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#define SJA1000_MAX_IRQ 20 /* max. number of interrupts handled in ISR */
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/* SJA1000 registers - manual section 6.4 (Pelican Mode) */
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#define SJA1000_MOD 0x00
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#define SJA1000_CMR 0x01
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#define SJA1000_SR 0x02
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#define SJA1000_IR 0x03
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#define SJA1000_IER 0x04
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#define SJA1000_ALC 0x0B
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#define SJA1000_ECC 0x0C
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#define SJA1000_EWL 0x0D
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#define SJA1000_RXERR 0x0E
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#define SJA1000_TXERR 0x0F
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#define SJA1000_ACCC0 0x10
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#define SJA1000_ACCC1 0x11
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#define SJA1000_ACCC2 0x12
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#define SJA1000_ACCC3 0x13
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#define SJA1000_ACCM0 0x14
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#define SJA1000_ACCM1 0x15
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#define SJA1000_ACCM2 0x16
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#define SJA1000_ACCM3 0x17
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#define SJA1000_RMC 0x1D
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#define SJA1000_RBSA 0x1E
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/* Common registers - manual section 6.5 */
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#define SJA1000_BTR0 0x06
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#define SJA1000_BTR1 0x07
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#define SJA1000_OCR 0x08
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#define SJA1000_CDR 0x1F
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#define SJA1000_FI 0x10
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#define SJA1000_SFF_BUF 0x13
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#define SJA1000_EFF_BUF 0x15
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#define SJA1000_FI_FF 0x80
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#define SJA1000_FI_RTR 0x40
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#define SJA1000_ID1 0x11
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#define SJA1000_ID2 0x12
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#define SJA1000_ID3 0x13
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#define SJA1000_ID4 0x14
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#define SJA1000_CAN_RAM 0x20
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/* mode register */
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#define MOD_RM 0x01
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#define MOD_LOM 0x02
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#define MOD_STM 0x04
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#define MOD_AFM 0x08
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#define MOD_SM 0x10
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/* commands */
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#define CMD_SRR 0x10
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#define CMD_CDO 0x08
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#define CMD_RRB 0x04
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#define CMD_AT 0x02
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#define CMD_TR 0x01
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/* interrupt sources */
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#define IRQ_BEI 0x80
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#define IRQ_ALI 0x40
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#define IRQ_EPI 0x20
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#define IRQ_WUI 0x10
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#define IRQ_DOI 0x08
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#define IRQ_EI 0x04
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#define IRQ_TI 0x02
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#define IRQ_RI 0x01
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#define IRQ_ALL 0xFF
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#define IRQ_OFF 0x00
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/* status register content */
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#define SR_BS 0x80
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#define SR_ES 0x40
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#define SR_TS 0x20
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#define SR_RS 0x10
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#define SR_TCS 0x08
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#define SR_TBS 0x04
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#define SR_DOS 0x02
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#define SR_RBS 0x01
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#define SR_CRIT (SR_BS|SR_ES)
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/* ECC register */
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#define ECC_SEG 0x1F
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#define ECC_DIR 0x20
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#define ECC_ERR 6
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#define ECC_BIT 0x00
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#define ECC_FORM 0x40
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#define ECC_STUFF 0x80
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#define ECC_MASK 0xc0
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/*
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* Flags for sja1000priv.flags
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*/
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#define SJA1000_CUSTOM_IRQ_HANDLER BIT(0)
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#define SJA1000_QUIRK_NO_CDR_REG BIT(1)
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/*
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* SJA1000 private data structure
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*/
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struct sja1000_priv {
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struct can_priv can; /* must be the first member */
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struct sk_buff *echo_skb;
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/* the lower-layer is responsible for appropriate locking */
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u8 (*read_reg) (const struct sja1000_priv *priv, int reg);
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void (*write_reg) (const struct sja1000_priv *priv, int reg, u8 val);
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void (*pre_irq) (const struct sja1000_priv *priv);
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void (*post_irq) (const struct sja1000_priv *priv);
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void *priv; /* for board-specific data */
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struct net_device *dev;
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void __iomem *reg_base; /* ioremap'ed address to registers */
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unsigned long irq_flags; /* for request_irq() */
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spinlock_t cmdreg_lock; /* lock for concurrent cmd register writes */
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u16 flags; /* custom mode flags */
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u8 ocr; /* output control register */
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u8 cdr; /* clock divider register */
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};
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struct net_device *alloc_sja1000dev(int sizeof_priv);
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void free_sja1000dev(struct net_device *dev);
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int register_sja1000dev(struct net_device *dev);
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void unregister_sja1000dev(struct net_device *dev);
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irqreturn_t sja1000_interrupt(int irq, void *dev_id);
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#endif /* SJA1000_DEV_H */
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