Andy Shevchenko 553e9c1861 platform/x86: intel_mid_powerbtn: Acknowledge interrupts ... Some platforms require interrupt to be acknowledged by clearing MSIC_PWRBTNM bit in interrupt level 1 mask register. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>		2017-02-04 02:47:23 +01:00
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chrome	platform/chrome: cros_ec_dev - Register cros-ec sensors	2016-10-25 18:20:32 +01:00
goldfish	platform: goldfish: pipe: use get_user_pages_unlocked()	2016-11-10 15:34:56 +01:00
mips	Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus	2016-05-19 10:02:26 -07:00
olpc	platform/olpc: Make ec explicitly non-modular	2016-08-28 22:31:52 -07:00
x86	platform/x86: intel_mid_powerbtn: Acknowledge interrupts	2017-02-04 02:47:23 +01:00
Kconfig	goldfish: refactor goldfish platform configs	2016-01-28 23:34:36 -08:00
Makefile	MIPS: Loongson-3: Add CPU Hwmon platform driver	2015-04-01 17:22:17 +02:00