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ce2fce2513
Several of our i915 header files, have been including i915_reg.h. This means that any change to i915_reg.h will trigger a full rebuild of pretty much every file of the driver, even those that don't have any kind of register access. Let's delete the i915_reg.h include from all headers and add an explicit include from the .c files that truly need the register definitions; those that need a definition of i915_reg_t for a function definition can get it from i915_reg_defs.h instead. We also remove two non-register #define's (VLV_DISPLAY_BASE and GEN12_SFC_DONE_MAX) into i915_reg_defs.h to allow us to drop the i915_reg.h include from a couple of headers. There's probably a lot more header dependency optimization possible, but the changes here roughly cut the number of files compiled after 'touch i915_reg.h' in half --- a good first step. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220127234334.4016964-7-matthew.d.roper@intel.com
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DE_H__
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#define __INTEL_DE_H__
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_uncore.h"
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static inline u32
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intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
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{
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return intel_uncore_read(&i915->uncore, reg);
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}
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static inline void
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intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
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{
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intel_uncore_posting_read(&i915->uncore, reg);
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}
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static inline void
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intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
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{
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intel_uncore_write(&i915->uncore, reg, val);
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}
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static inline void
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intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
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{
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intel_uncore_rmw(&i915->uncore, reg, clear, set);
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}
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static inline int
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intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout)
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{
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return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
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}
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static inline int
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intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, unsigned int timeout)
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{
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return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
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}
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static inline int
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intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, unsigned int timeout)
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{
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return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
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}
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/*
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* Unlocked mmio-accessors, think carefully before using these.
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*
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* Certain architectures will die if the same cacheline is concurrently accessed
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* by different clients (e.g. on Ivybridge). Access to registers should
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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static inline u32
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intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
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{
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u32 val;
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val = intel_uncore_read_fw(&i915->uncore, reg);
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trace_i915_reg_rw(false, reg, val, sizeof(val), true);
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return val;
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}
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static inline void
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intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
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{
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trace_i915_reg_rw(true, reg, val, sizeof(val), true);
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intel_uncore_write_fw(&i915->uncore, reg, val);
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}
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#endif /* __INTEL_DE_H__ */
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