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3b6f409547
Frontbuffer rendering and page flips can race with each other and this can potentialy cause issues with PSR2 selective fetch. And because pipe/crtc updates are time sentive we can't grab the PSR lock after intel_pipe_update_start() and before intel_pipe_update_end(). So here adding the lock and unlock functions and calls, the proper PSR2 selective fetch handling will come in a separated patch. v2: - fixed new functions documentation Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220405155344.47219-2-jose.souza@intel.com
61 lines
2.3 KiB
C
61 lines
2.3 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_PSR_H__
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#define __INTEL_PSR_H__
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#include <linux/types.h>
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enum fb_op_origin;
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struct drm_connector;
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struct drm_connector_state;
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_dp;
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struct intel_encoder;
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struct intel_plane;
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struct intel_plane_state;
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void intel_psr_init_dpcd(struct intel_dp *intel_dp);
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void intel_psr_pre_plane_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_psr_post_plane_update(const struct intel_atomic_state *state);
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void intel_psr_disable(struct intel_dp *intel_dp,
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const struct intel_crtc_state *old_crtc_state);
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int intel_psr_debug_set(struct intel_dp *intel_dp, u64 value);
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void intel_psr_invalidate(struct drm_i915_private *dev_priv,
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unsigned frontbuffer_bits,
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enum fb_op_origin origin);
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void intel_psr_flush(struct drm_i915_private *dev_priv,
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unsigned frontbuffer_bits,
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enum fb_op_origin origin);
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void intel_psr_init(struct intel_dp *intel_dp);
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void intel_psr_compute_config(struct intel_dp *intel_dp,
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struct intel_crtc_state *crtc_state,
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struct drm_connector_state *conn_state);
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void intel_psr_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config);
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void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
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void intel_psr_short_pulse(struct intel_dp *intel_dp);
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void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state);
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bool intel_psr_enabled(struct intel_dp *intel_dp);
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int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
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void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *plane_state,
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int color_plane);
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void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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void intel_psr_pause(struct intel_dp *intel_dp);
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void intel_psr_resume(struct intel_dp *intel_dp);
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void intel_psr_lock(const struct intel_crtc_state *crtc_state);
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void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
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#endif /* __INTEL_PSR_H__ */
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