Jesse Brandeburg 945a51517c intel drivers: repair missing flush operations ... after review of all intel drivers, found several instances where drivers had the incorrect pattern of: memory mapped write(); delay(); which should always be: memory mapped write(); write flush(); /* aka memory mapped read */ delay(); explanation: The reason for including the flush is that writes can be held (posted) in PCI/PCIe bridges, but the read always has to complete synchronously and therefore has to flush all pending writes to a device. If a write is held and followed by a delay, the delay means nothing because the write may not have reached hardware (maybe even not until the next read) Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>		2011-08-04 04:59:07 -07:00
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ixgb.h	ixgb: convert to set_phys_id	2011-05-04 12:07:41 -07:00
ixgb_ee.c	intel drivers: repair missing flush operations	2011-08-04 04:59:07 -07:00
ixgb_ee.h
ixgb_ethtool.c	ixgb: convert to set_phys_id	2011-05-04 12:07:41 -07:00
ixgb_hw.c	intel drivers: repair missing flush operations	2011-08-04 04:59:07 -07:00
ixgb_hw.h	ixgb: Use pr_<level> and netdev_<level>	2010-04-27 12:53:30 -07:00
ixgb_ids.h
ixgb_main.c	Add appropriate <linux/prefetch.h> include for prefetch users	2011-05-22 21:41:57 -07:00
ixgb_osdep.h	ixgb: Use pr_<level> and netdev_<level>	2010-04-27 12:53:30 -07:00
ixgb_param.c	Intel Wired LAN drivers: Use static const	2010-12-10 22:12:32 -08:00
Makefile