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![Hans de Goede](/assets/img/avatar_default.png)
The old implementation of sun9i_a80_get_pll4_factors() has several issues, it checks against 256 / 512 in various places where it should use 255 / 511, it does the wrong thing for low frequencies which are an even multiple of 6 MHz, e.g. if you ask it for 72 MHz it will result in 144 Mhz, and it does not take into account that n must be at least 12. Moreover it is quite hard to read / follow it. This commit rewrites it to be correct in all cases, and makes it much easier to follow the code / to read. Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
322 lines
7.1 KiB
C
322 lines
7.1 KiB
C
/*
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* Copyright 2014 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/log2.h>
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#include "clk-factors.h"
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/**
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* sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
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* PLL4 rate is calculated as follows
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* rate = (parent_rate * n >> p) / (m + 1);
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* parent_rate is always 24MHz
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*
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* p and m are named div1 and div2 in Allwinner's SDK
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*/
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static void sun9i_a80_get_pll4_factors(u32 *freq, u32 parent_rate,
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u8 *n_ret, u8 *k, u8 *m_ret, u8 *p_ret)
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{
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int n;
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int m = 1;
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int p = 1;
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/* Normalize value to a 6 MHz multiple (24 MHz / 4) */
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n = DIV_ROUND_UP(*freq, 6000000);
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/* If n is too large switch to steps of 12 MHz */
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if (n > 255) {
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m = 0;
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n = (n + 1) / 2;
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}
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/* If n is still too large switch to steps of 24 MHz */
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if (n > 255) {
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p = 0;
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n = (n + 1) / 2;
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}
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/* n must be between 12 and 255 */
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if (n > 255)
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n = 255;
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else if (n < 12)
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n = 12;
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*freq = ((24000000 * n) >> p) / (m + 1);
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/* we were called to round the frequency, we can now return */
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if (n_ret == NULL)
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return;
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*n_ret = n;
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*m_ret = m;
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*p_ret = p;
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}
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static struct clk_factors_config sun9i_a80_pll4_config = {
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.mshift = 18,
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.mwidth = 1,
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.nshift = 8,
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.nwidth = 8,
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.pshift = 16,
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.pwidth = 1,
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};
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static const struct factors_data sun9i_a80_pll4_data __initconst = {
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.enable = 31,
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.table = &sun9i_a80_pll4_config,
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.getter = sun9i_a80_get_pll4_factors,
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};
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static DEFINE_SPINLOCK(sun9i_a80_pll4_lock);
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static void __init sun9i_a80_pll4_setup(struct device_node *node)
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{
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void __iomem *reg;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (!reg) {
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pr_err("Could not get registers for a80-pll4-clk: %s\n",
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node->name);
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return;
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}
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sunxi_factors_register(node, &sun9i_a80_pll4_data,
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&sun9i_a80_pll4_lock, reg);
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}
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CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
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/**
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* sun9i_a80_get_gt_factors() - calculates m factor for GT
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* GT rate is calculated as follows
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* rate = parent_rate / (m + 1);
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*/
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static void sun9i_a80_get_gt_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u32 div;
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if (parent_rate < *freq)
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*freq = parent_rate;
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div = DIV_ROUND_UP(parent_rate, *freq);
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/* maximum divider is 4 */
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if (div > 4)
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div = 4;
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*freq = parent_rate / div;
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/* we were called to round the frequency, we can now return */
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if (!m)
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return;
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*m = div;
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}
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static struct clk_factors_config sun9i_a80_gt_config = {
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.mshift = 0,
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.mwidth = 2,
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};
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static const struct factors_data sun9i_a80_gt_data __initconst = {
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.mux = 24,
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.muxmask = BIT(1) | BIT(0),
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.table = &sun9i_a80_gt_config,
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.getter = sun9i_a80_get_gt_factors,
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};
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static DEFINE_SPINLOCK(sun9i_a80_gt_lock);
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static void __init sun9i_a80_gt_setup(struct device_node *node)
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{
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void __iomem *reg;
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struct clk *gt;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (!reg) {
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pr_err("Could not get registers for a80-gt-clk: %s\n",
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node->name);
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return;
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}
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gt = sunxi_factors_register(node, &sun9i_a80_gt_data,
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&sun9i_a80_gt_lock, reg);
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/* The GT bus clock needs to be always enabled */
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__clk_get(gt);
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clk_prepare_enable(gt);
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}
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CLK_OF_DECLARE(sun9i_a80_gt, "allwinner,sun9i-a80-gt-clk", sun9i_a80_gt_setup);
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/**
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* sun9i_a80_get_ahb_factors() - calculates p factor for AHB0/1/2
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* AHB rate is calculated as follows
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* rate = parent_rate >> p;
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*/
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static void sun9i_a80_get_ahb_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u32 _p;
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if (parent_rate < *freq)
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*freq = parent_rate;
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_p = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
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/* maximum p is 3 */
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if (_p > 3)
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_p = 3;
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*freq = parent_rate >> _p;
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/* we were called to round the frequency, we can now return */
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if (!p)
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return;
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*p = _p;
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}
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static struct clk_factors_config sun9i_a80_ahb_config = {
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.pshift = 0,
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.pwidth = 2,
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};
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static const struct factors_data sun9i_a80_ahb_data __initconst = {
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.mux = 24,
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.muxmask = BIT(1) | BIT(0),
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.table = &sun9i_a80_ahb_config,
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.getter = sun9i_a80_get_ahb_factors,
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};
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static DEFINE_SPINLOCK(sun9i_a80_ahb_lock);
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static void __init sun9i_a80_ahb_setup(struct device_node *node)
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{
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void __iomem *reg;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (!reg) {
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pr_err("Could not get registers for a80-ahb-clk: %s\n",
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node->name);
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return;
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}
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sunxi_factors_register(node, &sun9i_a80_ahb_data,
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&sun9i_a80_ahb_lock, reg);
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}
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CLK_OF_DECLARE(sun9i_a80_ahb, "allwinner,sun9i-a80-ahb-clk", sun9i_a80_ahb_setup);
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static const struct factors_data sun9i_a80_apb0_data __initconst = {
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.mux = 24,
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.muxmask = BIT(0),
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.table = &sun9i_a80_ahb_config,
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.getter = sun9i_a80_get_ahb_factors,
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};
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static DEFINE_SPINLOCK(sun9i_a80_apb0_lock);
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static void __init sun9i_a80_apb0_setup(struct device_node *node)
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{
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void __iomem *reg;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (!reg) {
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pr_err("Could not get registers for a80-apb0-clk: %s\n",
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node->name);
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return;
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}
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sunxi_factors_register(node, &sun9i_a80_apb0_data,
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&sun9i_a80_apb0_lock, reg);
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}
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CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-clk", sun9i_a80_apb0_setup);
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/**
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* sun9i_a80_get_apb1_factors() - calculates m, p factors for APB1
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* APB1 rate is calculated as follows
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* rate = (parent_rate >> p) / (m + 1);
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*/
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static void sun9i_a80_get_apb1_factors(u32 *freq, u32 parent_rate,
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u8 *n, u8 *k, u8 *m, u8 *p)
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{
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u32 div;
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u8 calcm, calcp;
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if (parent_rate < *freq)
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*freq = parent_rate;
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div = DIV_ROUND_UP(parent_rate, *freq);
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/* Highest possible divider is 256 (p = 3, m = 31) */
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if (div > 256)
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div = 256;
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calcp = order_base_2(div);
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calcm = (parent_rate >> calcp) - 1;
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*freq = (parent_rate >> calcp) / (calcm + 1);
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/* we were called to round the frequency, we can now return */
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if (n == NULL)
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return;
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*m = calcm;
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*p = calcp;
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}
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static struct clk_factors_config sun9i_a80_apb1_config = {
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.mshift = 0,
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.mwidth = 5,
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.pshift = 16,
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.pwidth = 2,
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};
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static const struct factors_data sun9i_a80_apb1_data __initconst = {
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.mux = 24,
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.muxmask = BIT(0),
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.table = &sun9i_a80_apb1_config,
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.getter = sun9i_a80_get_apb1_factors,
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};
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static DEFINE_SPINLOCK(sun9i_a80_apb1_lock);
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static void __init sun9i_a80_apb1_setup(struct device_node *node)
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{
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void __iomem *reg;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (!reg) {
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pr_err("Could not get registers for a80-apb1-clk: %s\n",
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node->name);
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return;
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}
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sunxi_factors_register(node, &sun9i_a80_apb1_data,
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&sun9i_a80_apb1_lock, reg);
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}
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CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-clk", sun9i_a80_apb1_setup);
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