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1abf329a71
Batch buffer will be created through dsb-reg-write function which can have single/multiple request based on usecase and once the buffer is ready commit function will trigger the execution of the batch buffer. All the registers will be updated simultaneously. v1: Initial version. v2: Optimized code few places. (Chris) v3: USed DRM_ERROR for dsb head/tail programming failure. (Shashank) v4: reset ins_start_offset after commit. (Jani) Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190920115930.27829-8-animesh.manna@intel.com
52 lines
1,009 B
C
52 lines
1,009 B
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef _INTEL_DSB_H
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#define _INTEL_DSB_H
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#include <linux/types.h>
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#include "i915_reg.h"
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struct intel_crtc;
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struct i915_vma;
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enum dsb_id {
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INVALID_DSB = -1,
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DSB1,
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DSB2,
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DSB3,
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MAX_DSB_PER_PIPE
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};
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struct intel_dsb {
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atomic_t refcount;
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enum dsb_id id;
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u32 *cmd_buf;
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struct i915_vma *vma;
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/*
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* free_pos will point the first free entry position
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* and help in calculating tail of command buffer.
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*/
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int free_pos;
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/*
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* ins_start_offset will help to store start address of the dsb
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* instuction and help in identifying the batch of auto-increment
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* register.
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*/
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u32 ins_start_offset;
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};
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struct intel_dsb *
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intel_dsb_get(struct intel_crtc *crtc);
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void intel_dsb_put(struct intel_dsb *dsb);
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void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
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void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
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u32 val);
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void intel_dsb_commit(struct intel_dsb *dsb);
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#endif
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