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linux-stable/drivers/clk/sunxi-ng
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Maxime Ripard abea24218a clk: sunxi-ng: mux: Re-adjust parent rate 
Currently, the parent rate given back to the clock framework in our
request is the original parent rate we calculated before trying to round
the rate of our clock.

This works fine unless our clock also changes its parent rate, in which
case we will simply ignore that change and still use the previous parent
rate.

Create a new function to re-adjust the parent rate to take the pre-dividers
into account, and give that back to the clock framework.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07 15:32:14 +02:00
..
ccu-sun5i.c clk: sunxi-ng: sun5i: Fix mux width for csi clock 2017-03-06 10:25:56 +01:00
ccu-sun5i.h clk: sunxi-ng: Add sun5i CCU driver 2017-01-23 11:45:29 +01:00
ccu-sun6i-a31.c clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset 2017-05-14 08:27:17 +02:00
ccu-sun6i-a31.h clk: sunxi-ng: Add A31/A31s clocks 2016-08-25 22:31:43 +02:00
ccu-sun8i-a23-a33.h clk: sunxi-ng: Add A33 CCU support 2016-09-10 11:41:19 +02:00
ccu-sun8i-a23.c clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks 2016-11-11 21:47:36 +01:00
ccu-sun8i-a33.c Allwinner clock patches for 4.12 2017-04-19 09:02:00 -07:00
ccu-sun8i-de2.c clk: sunxi-ng: add support for DE2 CCU 2017-06-07 15:32:12 +02:00
ccu-sun8i-de2.h clk: sunxi-ng: add support for DE2 CCU 2017-06-07 15:32:12 +02:00
ccu-sun8i-h3.c clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver 2017-03-06 10:25:56 +01:00
ccu-sun8i-h3.h clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM 2017-05-31 21:57:27 +02:00
ccu-sun8i-r.c clk: sunxi-ng: fix PRCM CCU ir clk parent 2017-04-10 09:04:23 +02:00
ccu-sun8i-r.h clk: sunxi-ng: fix PRCM CCU CLK_NUMBER value 2017-04-10 09:04:33 +02:00
ccu-sun8i-v3s.c clk: sunxi-ng: v3s: Fix usb otg device reset bit 2017-05-14 08:27:17 +02:00
ccu-sun8i-v3s.h clk: sunxi-ng: add support for V3s CCU 2017-01-20 21:39:03 +01:00
ccu-sun9i-a80-de.c clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() 2017-02-06 15:01:29 -08:00
ccu-sun9i-a80-de.h clk: sunxi-ng: Add A80 Display Engine CCU 2017-01-30 08:38:30 +01:00
ccu-sun9i-a80-usb.c clk: sunxi-ng: Add A80 USB CCU 2017-01-30 08:37:51 +01:00
ccu-sun9i-a80-usb.h clk: sunxi-ng: Add A80 USB CCU 2017-01-30 08:37:51 +01:00
ccu-sun9i-a80.c clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code 2017-04-13 14:09:30 +02:00
ccu-sun9i-a80.h clk: sunxi-ng: Add A80 CCU 2017-01-30 08:37:30 +01:00
ccu-sun50i-a64.c clk: sunxi-ng: Fix div/mult settings for osc12M on A64 2017-03-20 09:49:43 +01:00
ccu-sun50i-a64.h clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM 2017-05-31 21:57:30 +02:00
ccu_common.c Allwinner clock patches for 4.12 2017-04-19 09:02:00 -07:00
ccu_common.h clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks 2017-04-13 11:22:02 +02:00
ccu_div.c clk: sunxi-ng: mux: Change pre-divider application function prototype 2017-06-07 15:32:13 +02:00
ccu_div.h clk: sunxi-ng: Implement factors offsets 2017-01-23 11:44:27 +01:00
ccu_frac.c clk: sunxi-ng: Rename the internal structures 2016-10-20 19:24:20 +02:00
ccu_frac.h clk: sunxi-ng: Rename the internal structures 2016-10-20 19:24:20 +02:00
ccu_gate.c clk: sunxi-ng: gate: Support common pre-dividers 2017-03-06 10:25:56 +01:00
ccu_gate.h clk: sunxi-ng: Add gate clock support 2016-07-08 18:04:38 -07:00
ccu_mp.c clk: sunxi-ng: mux: Change pre-divider application function prototype 2017-06-07 15:32:13 +02:00
ccu_mp.h clk: sunxi-ng: Rename the internal structures 2016-10-20 19:24:20 +02:00
ccu_mult.c clk: sunxi-ng: mux: Change pre-divider application function prototype 2017-06-07 15:32:13 +02:00
ccu_mult.h clk: sunxi-ng: mult: Support PLL lock detection 2017-04-05 09:01:41 +02:00
ccu_mux.c clk: sunxi-ng: mux: Re-adjust parent rate 2017-06-07 15:32:14 +02:00
ccu_mux.h clk: sunxi-ng: mux: Change pre-divider application function prototype 2017-06-07 15:32:13 +02:00
ccu_nk.c clk: sunxi-ng: use 1 as fallback for minimum multiplier 2017-04-13 14:09:25 +02:00
ccu_nk.h clk: sunxi-ng: Rename the internal structures 2016-10-20 19:24:20 +02:00
ccu_nkm.c clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate 2017-06-07 15:32:13 +02:00
ccu_nkm.h clk: sunxi-ng: Rename the internal structures 2016-10-20 19:24:20 +02:00
ccu_nkmp.c Allwinner clock changes, take 2 2017-04-21 19:19:46 -07:00
ccu_nkmp.h clk: sunxi-ng: Rename the internal structures 2016-10-20 19:24:20 +02:00
ccu_nm.c clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch 2017-04-13 14:09:28 +02:00
ccu_nm.h clk: sunxi-ng: Rename the internal structures 2016-10-20 19:24:20 +02:00
ccu_phase.c clk: sunxi-ng: Add phase clock support 2016-07-08 18:04:45 -07:00
ccu_phase.h clk: sunxi-ng: Add phase clock support 2016-07-08 18:04:45 -07:00
ccu_reset.c
ccu_reset.h clk: sunxi-ng: explicitly include linux/spinlock.h 2017-06-07 15:32:12 +02:00
Kconfig clk: sunxi-ng: add support for DE2 CCU 2017-06-07 15:32:12 +02:00
Makefile clk: sunxi-ng: add support for DE2 CCU 2017-06-07 15:32:12 +02:00