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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-19 09:04:57 +00:00
c553138fbd
Instead of __raw_*, define imx_* to *_relaxed and use those. Using imx_* was requested by Arnd because *_relaxed tends to indicate that the code was carefully reviewed to not require any synchronisation and otherwise be safe, which isn't the case here with the automatic conversion. The conversion itself was done using the following spatch (since that automatically adjusts the coding style unlike a simple search&replace). @@ expression E1, E2; @@ -__raw_writel(E1, E2) +imx_writel(E1, E2) @@ expression E1, E2; @@ -__raw_writew(E1, E2) +imx_writew(E1, E2) @@ expression E1; @@ -__raw_readl(E1) +imx_readl(E1) @@ expression E1; @@ -__raw_readw(E1) +imx_readw(E1) Signed-off-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
161 lines
3.2 KiB
C
161 lines
3.2 KiB
C
#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include "hardware.h"
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#include "common.h"
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unsigned int __mxc_cpu_type;
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EXPORT_SYMBOL(__mxc_cpu_type);
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static unsigned int imx_soc_revision;
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void mxc_set_cpu_type(unsigned int type)
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{
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__mxc_cpu_type = type;
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}
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void imx_set_soc_revision(unsigned int rev)
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{
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imx_soc_revision = rev;
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}
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unsigned int imx_get_soc_revision(void)
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{
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return imx_soc_revision;
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}
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void imx_print_silicon_rev(const char *cpu, int srev)
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{
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if (srev == IMX_CHIP_REVISION_UNKNOWN)
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pr_info("CPU identified as %s, unknown revision\n", cpu);
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else
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pr_info("CPU identified as %s, silicon rev %d.%d\n",
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cpu, (srev >> 4) & 0xf, srev & 0xf);
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}
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void __init imx_set_aips(void __iomem *base)
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{
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unsigned int reg;
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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imx_writel(0x77777777, base + 0x0);
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imx_writel(0x77777777, base + 0x4);
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/*
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* Set all OPACRx to be non-bufferable, to not require
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* supervisor privilege level for access, allow for
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* write access and untrusted master access.
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*/
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imx_writel(0x0, base + 0x40);
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imx_writel(0x0, base + 0x44);
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imx_writel(0x0, base + 0x48);
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imx_writel(0x0, base + 0x4C);
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reg = imx_readl(base + 0x50) & 0x00FFFFFF;
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imx_writel(reg, base + 0x50);
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}
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void __init imx_aips_allow_unprivileged_access(
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const char *compat)
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{
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void __iomem *aips_base_addr;
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struct device_node *np;
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for_each_compatible_node(np, NULL, compat) {
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aips_base_addr = of_iomap(np, 0);
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imx_set_aips(aips_base_addr);
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}
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}
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struct device * __init imx_soc_device_init(void)
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{
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struct soc_device_attribute *soc_dev_attr;
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struct soc_device *soc_dev;
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struct device_node *root;
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const char *soc_id;
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int ret;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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return NULL;
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soc_dev_attr->family = "Freescale i.MX";
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root = of_find_node_by_path("/");
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ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
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of_node_put(root);
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if (ret)
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goto free_soc;
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switch (__mxc_cpu_type) {
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case MXC_CPU_MX1:
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soc_id = "i.MX1";
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break;
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case MXC_CPU_MX21:
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soc_id = "i.MX21";
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break;
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case MXC_CPU_MX25:
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soc_id = "i.MX25";
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break;
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case MXC_CPU_MX27:
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soc_id = "i.MX27";
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break;
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case MXC_CPU_MX31:
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soc_id = "i.MX31";
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break;
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case MXC_CPU_MX35:
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soc_id = "i.MX35";
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break;
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case MXC_CPU_MX51:
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soc_id = "i.MX51";
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break;
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case MXC_CPU_MX53:
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soc_id = "i.MX53";
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break;
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case MXC_CPU_IMX6SL:
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soc_id = "i.MX6SL";
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break;
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case MXC_CPU_IMX6DL:
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soc_id = "i.MX6DL";
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break;
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case MXC_CPU_IMX6SX:
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soc_id = "i.MX6SX";
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break;
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case MXC_CPU_IMX6Q:
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soc_id = "i.MX6Q";
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break;
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case MXC_CPU_IMX6UL:
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soc_id = "i.MX6UL";
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break;
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case MXC_CPU_IMX7D:
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soc_id = "i.MX7D";
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break;
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default:
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soc_id = "Unknown";
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}
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soc_dev_attr->soc_id = soc_id;
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soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
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(imx_soc_revision >> 4) & 0xf,
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imx_soc_revision & 0xf);
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if (!soc_dev_attr->revision)
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goto free_soc;
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev))
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goto free_rev;
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return soc_device_to_device(soc_dev);
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free_rev:
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kfree(soc_dev_attr->revision);
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free_soc:
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kfree(soc_dev_attr);
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return NULL;
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}
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