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![Tvrtko Ursulin](/assets/img/avatar_default.png)
These functions operate on ggtt so make them take that directly as parameter. At the same time move the USES_GUC conditional down to intel_guc_reserve_ggtt_top for symmetry with intel_guc_reserved_gtt_size. v2: * Rename and move functions to be static in i915_gem_gtt.c (Michal) v3: * Add comment explaining reason for reservation, add assert and fix error message. (Michal) v4: * Fix checkpatch error. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190611122350.15060-1-tvrtko.ursulin@linux.intel.com
687 lines
19 KiB
C
687 lines
19 KiB
C
/*
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* Copyright © 2014-2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "intel_guc.h"
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#include "intel_guc_ads.h"
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#include "intel_guc_submission.h"
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#include "i915_drv.h"
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static void gen8_guc_raise_irq(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
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}
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static void gen11_guc_raise_irq(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
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}
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static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
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{
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GEM_BUG_ON(!guc->send_regs.base);
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GEM_BUG_ON(!guc->send_regs.count);
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GEM_BUG_ON(i >= guc->send_regs.count);
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return _MMIO(guc->send_regs.base + 4 * i);
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}
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void intel_guc_init_send_regs(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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enum forcewake_domains fw_domains = 0;
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unsigned int i;
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if (INTEL_GEN(dev_priv) >= 11) {
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guc->send_regs.base =
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i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
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guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
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} else {
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guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
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guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
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BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
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}
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for (i = 0; i < guc->send_regs.count; i++) {
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fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
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guc_send_reg(guc, i),
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FW_REG_READ | FW_REG_WRITE);
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}
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guc->send_regs.fw_domains = fw_domains;
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}
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void intel_guc_init_early(struct intel_guc *guc)
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{
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struct drm_i915_private *i915 = guc_to_i915(guc);
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intel_guc_fw_init_early(guc);
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intel_guc_ct_init_early(&guc->ct);
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intel_guc_log_init_early(&guc->log);
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mutex_init(&guc->send_mutex);
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spin_lock_init(&guc->irq_lock);
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guc->send = intel_guc_send_nop;
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guc->handler = intel_guc_to_host_event_handler_nop;
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if (INTEL_GEN(i915) >= 11) {
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guc->notify = gen11_guc_raise_irq;
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guc->interrupts.reset = gen11_reset_guc_interrupts;
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guc->interrupts.enable = gen11_enable_guc_interrupts;
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guc->interrupts.disable = gen11_disable_guc_interrupts;
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} else {
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guc->notify = gen8_guc_raise_irq;
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guc->interrupts.reset = gen9_reset_guc_interrupts;
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guc->interrupts.enable = gen9_enable_guc_interrupts;
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guc->interrupts.disable = gen9_disable_guc_interrupts;
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}
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}
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static int guc_init_wq(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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/*
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* GuC log buffer flush work item has to do register access to
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* send the ack to GuC and this work item, if not synced before
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* suspend, can potentially get executed after the GFX device is
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* suspended.
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* By marking the WQ as freezable, we don't have to bother about
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* flushing of this work item from the suspend hooks, the pending
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* work item if any will be either executed before the suspend
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* or scheduled later on resume. This way the handling of work
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* item can be kept same between system suspend & rpm suspend.
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*/
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guc->log.relay.flush_wq =
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alloc_ordered_workqueue("i915-guc_log",
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WQ_HIGHPRI | WQ_FREEZABLE);
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if (!guc->log.relay.flush_wq) {
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DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
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return -ENOMEM;
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}
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/*
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* Even though both sending GuC action, and adding a new workitem to
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* GuC workqueue are serialized (each with its own locking), since
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* we're using mutliple engines, it's possible that we're going to
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* issue a preempt request with two (or more - each for different
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* engine) workitems in GuC queue. In this situation, GuC may submit
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* all of them, which will make us very confused.
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* Our preemption contexts may even already be complete - before we
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* even had the chance to sent the preempt action to GuC!. Rather
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* than introducing yet another lock, we can just use ordered workqueue
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* to make sure we're always sending a single preemption request with a
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* single workitem.
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*/
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if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
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USES_GUC_SUBMISSION(dev_priv)) {
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guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
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WQ_HIGHPRI);
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if (!guc->preempt_wq) {
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destroy_workqueue(guc->log.relay.flush_wq);
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DRM_ERROR("Couldn't allocate workqueue for GuC "
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"preemption\n");
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return -ENOMEM;
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}
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}
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return 0;
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}
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static void guc_fini_wq(struct intel_guc *guc)
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{
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struct workqueue_struct *wq;
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wq = fetch_and_zero(&guc->preempt_wq);
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if (wq)
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destroy_workqueue(wq);
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wq = fetch_and_zero(&guc->log.relay.flush_wq);
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if (wq)
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destroy_workqueue(wq);
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}
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int intel_guc_init_misc(struct intel_guc *guc)
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{
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struct drm_i915_private *i915 = guc_to_i915(guc);
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int ret;
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ret = guc_init_wq(guc);
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if (ret)
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return ret;
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intel_uc_fw_fetch(i915, &guc->fw);
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return 0;
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}
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void intel_guc_fini_misc(struct intel_guc *guc)
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{
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intel_uc_fw_cleanup_fetch(&guc->fw);
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guc_fini_wq(guc);
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}
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static int guc_shared_data_create(struct intel_guc *guc)
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{
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struct i915_vma *vma;
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void *vaddr;
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vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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i915_vma_unpin_and_release(&vma, 0);
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return PTR_ERR(vaddr);
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}
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guc->shared_data = vma;
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guc->shared_data_vaddr = vaddr;
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return 0;
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}
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static void guc_shared_data_destroy(struct intel_guc *guc)
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{
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i915_vma_unpin_and_release(&guc->shared_data, I915_VMA_RELEASE_MAP);
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}
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int intel_guc_init(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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int ret;
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ret = intel_uc_fw_init(&guc->fw);
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if (ret)
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goto err_fetch;
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ret = guc_shared_data_create(guc);
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if (ret)
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goto err_fw;
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GEM_BUG_ON(!guc->shared_data);
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ret = intel_guc_log_create(&guc->log);
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if (ret)
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goto err_shared;
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ret = intel_guc_ads_create(guc);
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if (ret)
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goto err_log;
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GEM_BUG_ON(!guc->ads_vma);
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ret = intel_guc_ct_init(&guc->ct);
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if (ret)
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goto err_ads;
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/* We need to notify the guc whenever we change the GGTT */
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i915_ggtt_enable_guc(dev_priv);
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return 0;
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err_ads:
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intel_guc_ads_destroy(guc);
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err_log:
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intel_guc_log_destroy(&guc->log);
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err_shared:
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guc_shared_data_destroy(guc);
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err_fw:
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intel_uc_fw_fini(&guc->fw);
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err_fetch:
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intel_uc_fw_cleanup_fetch(&guc->fw);
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return ret;
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}
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void intel_guc_fini(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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i915_ggtt_disable_guc(dev_priv);
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intel_guc_ct_fini(&guc->ct);
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intel_guc_ads_destroy(guc);
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intel_guc_log_destroy(&guc->log);
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guc_shared_data_destroy(guc);
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intel_uc_fw_fini(&guc->fw);
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intel_uc_fw_cleanup_fetch(&guc->fw);
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}
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static u32 guc_ctl_debug_flags(struct intel_guc *guc)
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{
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u32 level = intel_guc_log_get_level(&guc->log);
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u32 flags = 0;
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if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
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flags |= GUC_LOG_DISABLED;
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else
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flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
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GUC_LOG_VERBOSITY_SHIFT;
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return flags;
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}
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static u32 guc_ctl_feature_flags(struct intel_guc *guc)
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{
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u32 flags = 0;
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if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
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flags |= GUC_CTL_DISABLE_SCHEDULER;
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return flags;
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}
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static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
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{
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u32 flags = 0;
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if (USES_GUC_SUBMISSION(guc_to_i915(guc))) {
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u32 ctxnum, base;
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base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
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ctxnum = GUC_MAX_STAGE_DESCRIPTORS / 16;
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base >>= PAGE_SHIFT;
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flags |= (base << GUC_CTL_BASE_ADDR_SHIFT) |
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(ctxnum << GUC_CTL_CTXNUM_IN16_SHIFT);
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}
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return flags;
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}
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static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
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{
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u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
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u32 flags;
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#if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)
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#define UNIT SZ_1M
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#define FLAG GUC_LOG_ALLOC_IN_MEGABYTE
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#else
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#define UNIT SZ_4K
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#define FLAG 0
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#endif
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BUILD_BUG_ON(!CRASH_BUFFER_SIZE);
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BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT));
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BUILD_BUG_ON(!DPC_BUFFER_SIZE);
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BUILD_BUG_ON(!IS_ALIGNED(DPC_BUFFER_SIZE, UNIT));
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BUILD_BUG_ON(!ISR_BUFFER_SIZE);
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BUILD_BUG_ON(!IS_ALIGNED(ISR_BUFFER_SIZE, UNIT));
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BUILD_BUG_ON((CRASH_BUFFER_SIZE / UNIT - 1) >
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(GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));
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BUILD_BUG_ON((DPC_BUFFER_SIZE / UNIT - 1) >
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(GUC_LOG_DPC_MASK >> GUC_LOG_DPC_SHIFT));
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BUILD_BUG_ON((ISR_BUFFER_SIZE / UNIT - 1) >
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(GUC_LOG_ISR_MASK >> GUC_LOG_ISR_SHIFT));
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flags = GUC_LOG_VALID |
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GUC_LOG_NOTIFY_ON_HALF_FULL |
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FLAG |
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((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) |
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((DPC_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DPC_SHIFT) |
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((ISR_BUFFER_SIZE / UNIT - 1) << GUC_LOG_ISR_SHIFT) |
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(offset << GUC_LOG_BUF_ADDR_SHIFT);
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#undef UNIT
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#undef FLAG
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return flags;
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}
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static u32 guc_ctl_ads_flags(struct intel_guc *guc)
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{
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u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
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u32 flags = ads << GUC_ADS_ADDR_SHIFT;
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return flags;
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}
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/*
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* Initialise the GuC parameter block before starting the firmware
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* transfer. These parameters are read by the firmware on startup
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* and cannot be changed thereafter.
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*/
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void intel_guc_init_params(struct intel_guc *guc)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 params[GUC_CTL_MAX_DWORDS];
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int i;
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memset(params, 0, sizeof(params));
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params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
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params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
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params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
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params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
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params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
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for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
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DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
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/*
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* All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
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* they are power context saved so it's ok to release forcewake
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* when we are done here and take it again at xfer time.
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*/
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intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_BLITTER);
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I915_WRITE(SOFT_SCRATCH(0), 0);
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for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
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I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
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}
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int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
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u32 *response_buf, u32 response_buf_size)
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{
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WARN(1, "Unexpected send: action=%#x\n", *action);
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return -ENODEV;
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}
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void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
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{
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WARN(1, "Unexpected event: no suitable handler\n");
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}
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/*
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* This function implements the MMIO based host to GuC interface.
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*/
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int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
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u32 *response_buf, u32 response_buf_size)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_uncore *uncore = &dev_priv->uncore;
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u32 status;
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int i;
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int ret;
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GEM_BUG_ON(!len);
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GEM_BUG_ON(len > guc->send_regs.count);
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/* We expect only action code */
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GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK);
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/* If CT is available, we expect to use MMIO only during init/fini */
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GEM_BUG_ON(*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
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*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
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mutex_lock(&guc->send_mutex);
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intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
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for (i = 0; i < len; i++)
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intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]);
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intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
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intel_guc_notify(guc);
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/*
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* No GuC command should ever take longer than 10ms.
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* Fast commands should still complete in 10us.
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*/
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ret = __intel_wait_for_register_fw(uncore,
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guc_send_reg(guc, 0),
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INTEL_GUC_MSG_TYPE_MASK,
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INTEL_GUC_MSG_TYPE_RESPONSE <<
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INTEL_GUC_MSG_TYPE_SHIFT,
|
|
10, 10, &status);
|
|
/* If GuC explicitly returned an error, convert it to -EIO */
|
|
if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status))
|
|
ret = -EIO;
|
|
|
|
if (ret) {
|
|
DRM_ERROR("MMIO: GuC action %#x failed with error %d %#x\n",
|
|
action[0], ret, status);
|
|
goto out;
|
|
}
|
|
|
|
if (response_buf) {
|
|
int count = min(response_buf_size, guc->send_regs.count - 1);
|
|
|
|
for (i = 0; i < count; i++)
|
|
response_buf[i] = I915_READ(guc_send_reg(guc, i + 1));
|
|
}
|
|
|
|
/* Use data from the GuC response as our return value */
|
|
ret = INTEL_GUC_MSG_TO_DATA(status);
|
|
|
|
out:
|
|
intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);
|
|
mutex_unlock(&guc->send_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
|
|
const u32 *payload, u32 len)
|
|
{
|
|
u32 msg;
|
|
|
|
if (unlikely(!len))
|
|
return -EPROTO;
|
|
|
|
/* Make sure to handle only enabled messages */
|
|
msg = payload[0] & guc->msg_enabled_mask;
|
|
|
|
if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
|
|
INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
|
|
intel_guc_log_handle_flush_event(&guc->log);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int intel_guc_sample_forcewake(struct intel_guc *guc)
|
|
{
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
u32 action[2];
|
|
|
|
action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
|
|
/* WaRsDisableCoarsePowerGating:skl,cnl */
|
|
if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
|
|
action[1] = 0;
|
|
else
|
|
/* bit 0 and 1 are for Render and Media domain separately */
|
|
action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
|
|
|
|
return intel_guc_send(guc, action, ARRAY_SIZE(action));
|
|
}
|
|
|
|
/**
|
|
* intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
|
|
* @guc: intel_guc structure
|
|
* @rsa_offset: rsa offset w.r.t ggtt base of huc vma
|
|
*
|
|
* Triggers a HuC firmware authentication request to the GuC via intel_guc_send
|
|
* INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
|
|
* intel_huc_auth().
|
|
*
|
|
* Return: non-zero code on error
|
|
*/
|
|
int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
|
|
{
|
|
u32 action[] = {
|
|
INTEL_GUC_ACTION_AUTHENTICATE_HUC,
|
|
rsa_offset
|
|
};
|
|
|
|
return intel_guc_send(guc, action, ARRAY_SIZE(action));
|
|
}
|
|
|
|
/**
|
|
* intel_guc_suspend() - notify GuC entering suspend state
|
|
* @guc: the guc
|
|
*/
|
|
int intel_guc_suspend(struct intel_guc *guc)
|
|
{
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
int ret;
|
|
u32 status;
|
|
u32 action[] = {
|
|
INTEL_GUC_ACTION_ENTER_S_STATE,
|
|
GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
|
|
};
|
|
|
|
/*
|
|
* The ENTER_S_STATE action queues the save/restore operation in GuC FW
|
|
* and then returns, so waiting on the H2G is not enough to guarantee
|
|
* GuC is done. When all the processing is done, GuC writes
|
|
* INTEL_GUC_SLEEP_STATE_SUCCESS to scratch register 14, so we can poll
|
|
* on that. Note that GuC does not ensure that the value in the register
|
|
* is different from INTEL_GUC_SLEEP_STATE_SUCCESS while the action is
|
|
* in progress so we need to take care of that ourselves as well.
|
|
*/
|
|
|
|
I915_WRITE(SOFT_SCRATCH(14), INTEL_GUC_SLEEP_STATE_INVALID_MASK);
|
|
|
|
ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = __intel_wait_for_register(&dev_priv->uncore, SOFT_SCRATCH(14),
|
|
INTEL_GUC_SLEEP_STATE_INVALID_MASK,
|
|
0, 0, 10, &status);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (status != INTEL_GUC_SLEEP_STATE_SUCCESS) {
|
|
DRM_ERROR("GuC failed to change sleep state. "
|
|
"action=0x%x, err=%u\n",
|
|
action[0], status);
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* intel_guc_reset_engine() - ask GuC to reset an engine
|
|
* @guc: intel_guc structure
|
|
* @engine: engine to be reset
|
|
*/
|
|
int intel_guc_reset_engine(struct intel_guc *guc,
|
|
struct intel_engine_cs *engine)
|
|
{
|
|
u32 data[7];
|
|
|
|
GEM_BUG_ON(!guc->execbuf_client);
|
|
|
|
data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET;
|
|
data[1] = engine->guc_id;
|
|
data[2] = 0;
|
|
data[3] = 0;
|
|
data[4] = 0;
|
|
data[5] = guc->execbuf_client->stage_id;
|
|
data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
|
|
|
|
return intel_guc_send(guc, data, ARRAY_SIZE(data));
|
|
}
|
|
|
|
/**
|
|
* intel_guc_resume() - notify GuC resuming from suspend state
|
|
* @guc: the guc
|
|
*/
|
|
int intel_guc_resume(struct intel_guc *guc)
|
|
{
|
|
u32 action[] = {
|
|
INTEL_GUC_ACTION_EXIT_S_STATE,
|
|
GUC_POWER_D0,
|
|
};
|
|
|
|
return intel_guc_send(guc, action, ARRAY_SIZE(action));
|
|
}
|
|
|
|
/**
|
|
* DOC: GuC Address Space
|
|
*
|
|
* The layout of GuC address space is shown below:
|
|
*
|
|
* ::
|
|
*
|
|
* +===========> +====================+ <== FFFF_FFFF
|
|
* ^ | Reserved |
|
|
* | +====================+ <== GUC_GGTT_TOP
|
|
* | | |
|
|
* | | DRAM |
|
|
* GuC | |
|
|
* Address +===> +====================+ <== GuC ggtt_pin_bias
|
|
* Space ^ | |
|
|
* | | | |
|
|
* | GuC | GuC |
|
|
* | WOPCM | WOPCM |
|
|
* | Size | |
|
|
* | | | |
|
|
* v v | |
|
|
* +=======+===> +====================+ <== 0000_0000
|
|
*
|
|
* The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
|
|
* while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
|
|
* to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
|
|
*/
|
|
|
|
/**
|
|
* intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
|
|
* @guc: the guc
|
|
* @size: size of area to allocate (both virtual space and memory)
|
|
*
|
|
* This is a wrapper to create an object for use with the GuC. In order to
|
|
* use it inside the GuC, an object needs to be pinned lifetime, so we allocate
|
|
* both some backing storage and a range inside the Global GTT. We must pin
|
|
* it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
|
|
* range is reserved inside GuC.
|
|
*
|
|
* Return: A i915_vma if successful, otherwise an ERR_PTR.
|
|
*/
|
|
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
|
|
{
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
struct drm_i915_gem_object *obj;
|
|
struct i915_vma *vma;
|
|
u64 flags;
|
|
int ret;
|
|
|
|
obj = i915_gem_object_create_shmem(dev_priv, size);
|
|
if (IS_ERR(obj))
|
|
return ERR_CAST(obj);
|
|
|
|
vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
|
|
if (IS_ERR(vma))
|
|
goto err;
|
|
|
|
flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
|
|
ret = i915_vma_pin(vma, 0, 0, flags);
|
|
if (ret) {
|
|
vma = ERR_PTR(ret);
|
|
goto err;
|
|
}
|
|
|
|
return vma;
|
|
|
|
err:
|
|
i915_gem_object_put(obj);
|
|
return vma;
|
|
}
|