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clk-agilex.c
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clk: socfpga: agilex: add the bypass register for s2f_usr0 clock
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2021-07-26 17:56:21 -07:00 |
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clk-gate-a10.c
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clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return
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2021-04-07 16:29:31 -07:00 |
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clk-gate-s10.c
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clk: agilex/stratix10: add support for the 2nd bypass
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2021-06-27 16:39:59 -07:00 |
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clk-gate.c
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Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' and 'clk-qcom' into clk-next
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2021-04-27 16:34:28 -07:00 |
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clk-periph-a10.c
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clk: socfpga: arria10: convert to use clk_hw
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2021-03-30 19:26:26 -07:00 |
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clk-periph-s10.c
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clk: agilex/stratix10/n5x: fix how the bypass_reg is handled
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2021-06-27 16:39:59 -07:00 |
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clk-periph.c
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clk: socfpga: use clk_hw_register for a5/c5
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2021-03-30 19:26:26 -07:00 |
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clk-pll-a10.c
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clk: socfpga: arria10: convert to use clk_hw
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2021-03-30 19:26:26 -07:00 |
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clk-pll-s10.c
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clk: socfpga: remove redundant initialization of variable div
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2021-04-07 16:30:23 -07:00 |
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clk-pll.c
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clk: socfpga: clk-pll: Remove unused variable 'rc'
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2021-06-27 17:33:21 -07:00 |
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clk-s10.c
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clk: agilex/stratix10: fix bypass representation
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2021-06-27 16:39:59 -07:00 |
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clk.c
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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13
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2019-05-21 11:28:45 +02:00 |
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clk.h
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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288
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2019-06-05 17:36:37 +02:00 |
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Kconfig
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clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)
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2021-03-23 11:03:36 -05:00 |
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Makefile
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clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)
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2021-03-23 11:03:36 -05:00 |
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stratix10-clk.h
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clk: agilex/stratix10: add support for the 2nd bypass
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2021-06-27 16:39:59 -07:00 |
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