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62a7b9c859
To maintain the uniformity in accessing GCR registers, this patch modifies the S0ix counter read function to use GCR address base instead of ipc address base. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Tested-by: Shanth Murthy <shanth.murthy@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
84 lines
2 KiB
C
84 lines
2 KiB
C
#ifndef _ASM_X86_INTEL_PMC_IPC_H_
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#define _ASM_X86_INTEL_PMC_IPC_H_
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/* Commands */
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#define PMC_IPC_PMIC_ACCESS 0xFF
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#define PMC_IPC_PMIC_ACCESS_READ 0x0
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#define PMC_IPC_PMIC_ACCESS_WRITE 0x1
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#define PMC_IPC_USB_PWR_CTRL 0xF0
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#define PMC_IPC_PMIC_BLACKLIST_SEL 0xEF
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#define PMC_IPC_PHY_CONFIG 0xEE
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#define PMC_IPC_NORTHPEAK_CTRL 0xED
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#define PMC_IPC_PM_DEBUG 0xEC
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#define PMC_IPC_PMC_TELEMTRY 0xEB
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#define PMC_IPC_PMC_FW_MSG_CTRL 0xEA
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/* IPC return code */
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#define IPC_ERR_NONE 0
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#define IPC_ERR_CMD_NOT_SUPPORTED 1
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#define IPC_ERR_CMD_NOT_SERVICED 2
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#define IPC_ERR_UNABLE_TO_SERVICE 3
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#define IPC_ERR_CMD_INVALID 4
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#define IPC_ERR_CMD_FAILED 5
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#define IPC_ERR_EMSECURITY 6
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#define IPC_ERR_UNSIGNEDKERNEL 7
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/* GCR reg offsets from gcr base*/
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#define PMC_GCR_PMC_CFG_REG 0x08
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#define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78
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#define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80
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#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
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int intel_pmc_ipc_simple_command(int cmd, int sub);
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int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
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u32 *out, u32 outlen, u32 dptr, u32 sptr);
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int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
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u32 *out, u32 outlen);
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int intel_pmc_s0ix_counter_read(u64 *data);
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int intel_pmc_gcr_read(u32 offset, u32 *data);
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int intel_pmc_gcr_write(u32 offset, u32 data);
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int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val);
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#else
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static inline int intel_pmc_ipc_simple_command(int cmd, int sub)
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{
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return -EINVAL;
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}
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static inline int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
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u32 *out, u32 outlen, u32 dptr, u32 sptr)
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{
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return -EINVAL;
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}
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static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
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u32 *out, u32 outlen)
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{
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return -EINVAL;
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}
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static inline int intel_pmc_s0ix_counter_read(u64 *data)
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{
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return -EINVAL;
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}
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static inline int intel_pmc_gcr_read(u32 offset, u32 *data)
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{
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return -EINVAL;
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}
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static inline int intel_pmc_gcr_write(u32 offset, u32 data)
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{
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return -EINVAL;
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}
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static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
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{
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return -EINVAL;
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}
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#endif /*CONFIG_INTEL_PMC_IPC*/
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#endif
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