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![Rex Zhu](/assets/img/avatar_default.png)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
501 lines
15 KiB
C
501 lines
15 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_DPM_H__
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#define __AMDGPU_DPM_H__
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enum amdgpu_int_thermal_type {
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THERMAL_TYPE_NONE,
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THERMAL_TYPE_EXTERNAL,
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THERMAL_TYPE_EXTERNAL_GPIO,
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THERMAL_TYPE_RV6XX,
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THERMAL_TYPE_RV770,
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THERMAL_TYPE_ADT7473_WITH_INTERNAL,
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THERMAL_TYPE_EVERGREEN,
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THERMAL_TYPE_SUMO,
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THERMAL_TYPE_NI,
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THERMAL_TYPE_SI,
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THERMAL_TYPE_EMC2103_WITH_INTERNAL,
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THERMAL_TYPE_CI,
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THERMAL_TYPE_KV,
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};
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enum amdgpu_dpm_auto_throttle_src {
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AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
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AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
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};
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enum amdgpu_dpm_event_src {
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AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
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AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
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AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
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AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
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AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
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};
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#define SCLK_DEEP_SLEEP_MASK 0x8
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struct amdgpu_ps {
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u32 caps; /* vbios flags */
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u32 class; /* vbios flags */
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u32 class2; /* vbios flags */
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/* UVD clocks */
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u32 vclk;
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u32 dclk;
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/* VCE clocks */
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u32 evclk;
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u32 ecclk;
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bool vce_active;
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enum amd_vce_level vce_level;
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/* asic priv */
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void *ps_priv;
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};
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struct amdgpu_dpm_thermal {
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/* thermal interrupt work */
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struct work_struct work;
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/* low temperature threshold */
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int min_temp;
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/* high temperature threshold */
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int max_temp;
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/* was last interrupt low to high or high to low */
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bool high_to_low;
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/* interrupt source */
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struct amdgpu_irq_src irq;
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};
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enum amdgpu_clk_action
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{
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AMDGPU_SCLK_UP = 1,
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AMDGPU_SCLK_DOWN
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};
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struct amdgpu_blacklist_clocks
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{
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u32 sclk;
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u32 mclk;
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enum amdgpu_clk_action action;
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};
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struct amdgpu_clock_and_voltage_limits {
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u32 sclk;
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u32 mclk;
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u16 vddc;
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u16 vddci;
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};
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struct amdgpu_clock_array {
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u32 count;
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u32 *values;
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};
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struct amdgpu_clock_voltage_dependency_entry {
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u32 clk;
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u16 v;
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};
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struct amdgpu_clock_voltage_dependency_table {
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u32 count;
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struct amdgpu_clock_voltage_dependency_entry *entries;
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};
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union amdgpu_cac_leakage_entry {
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struct {
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u16 vddc;
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u32 leakage;
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};
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struct {
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u16 vddc1;
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u16 vddc2;
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u16 vddc3;
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};
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};
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struct amdgpu_cac_leakage_table {
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u32 count;
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union amdgpu_cac_leakage_entry *entries;
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};
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struct amdgpu_phase_shedding_limits_entry {
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u16 voltage;
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u32 sclk;
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u32 mclk;
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};
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struct amdgpu_phase_shedding_limits_table {
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u32 count;
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struct amdgpu_phase_shedding_limits_entry *entries;
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};
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struct amdgpu_uvd_clock_voltage_dependency_entry {
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u32 vclk;
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u32 dclk;
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u16 v;
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};
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struct amdgpu_uvd_clock_voltage_dependency_table {
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u8 count;
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struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
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};
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struct amdgpu_vce_clock_voltage_dependency_entry {
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u32 ecclk;
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u32 evclk;
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u16 v;
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};
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struct amdgpu_vce_clock_voltage_dependency_table {
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u8 count;
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struct amdgpu_vce_clock_voltage_dependency_entry *entries;
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};
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struct amdgpu_ppm_table {
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u8 ppm_design;
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u16 cpu_core_number;
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u32 platform_tdp;
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u32 small_ac_platform_tdp;
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u32 platform_tdc;
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u32 small_ac_platform_tdc;
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u32 apu_tdp;
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u32 dgpu_tdp;
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u32 dgpu_ulv_power;
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u32 tj_max;
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};
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struct amdgpu_cac_tdp_table {
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u16 tdp;
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u16 configurable_tdp;
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u16 tdc;
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u16 battery_power_limit;
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u16 small_power_limit;
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u16 low_cac_leakage;
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u16 high_cac_leakage;
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u16 maximum_power_delivery_limit;
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};
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struct amdgpu_dpm_dynamic_state {
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struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
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struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
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struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
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struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
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struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
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struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
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struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
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struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
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struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
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struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
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struct amdgpu_clock_array valid_sclk_values;
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struct amdgpu_clock_array valid_mclk_values;
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struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
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struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
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u32 mclk_sclk_ratio;
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u32 sclk_mclk_delta;
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u16 vddc_vddci_delta;
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u16 min_vddc_for_pcie_gen2;
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struct amdgpu_cac_leakage_table cac_leakage_table;
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struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
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struct amdgpu_ppm_table *ppm_table;
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struct amdgpu_cac_tdp_table *cac_tdp_table;
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};
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struct amdgpu_dpm_fan {
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u16 t_min;
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u16 t_med;
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u16 t_high;
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u16 pwm_min;
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u16 pwm_med;
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u16 pwm_high;
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u8 t_hyst;
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u32 cycle_delay;
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u16 t_max;
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u8 control_mode;
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u16 default_max_fan_pwm;
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u16 default_fan_output_sensitivity;
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u16 fan_output_sensitivity;
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bool ucode_fan_control;
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};
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enum amdgpu_pcie_gen {
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AMDGPU_PCIE_GEN1 = 0,
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AMDGPU_PCIE_GEN2 = 1,
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AMDGPU_PCIE_GEN3 = 2,
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AMDGPU_PCIE_GEN_INVALID = 0xffff
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};
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#define amdgpu_dpm_pre_set_power_state(adev) \
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((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_set_power_state(adev) \
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((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_post_set_power_state(adev) \
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((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_display_configuration_changed(adev) \
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((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_print_power_state(adev, ps) \
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((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
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#define amdgpu_dpm_vblank_too_short(adev) \
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((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_enable_bapm(adev, e) \
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((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
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#define amdgpu_dpm_read_sensor(adev, idx, value, size) \
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((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size)))
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#define amdgpu_dpm_get_temperature(adev) \
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((adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_set_fan_control_mode(adev, m) \
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((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))
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#define amdgpu_dpm_get_fan_control_mode(adev) \
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((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
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((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
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#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
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((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
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#define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
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((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
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#define amdgpu_dpm_get_sclk(adev, l) \
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((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))
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#define amdgpu_dpm_get_mclk(adev, l) \
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((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)))
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#define amdgpu_dpm_force_performance_level(adev, l) \
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((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
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#define amdgpu_dpm_powergate_uvd(adev, g) \
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((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
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#define amdgpu_dpm_powergate_vce(adev, g) \
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((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
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#define amdgpu_dpm_get_current_power_state(adev) \
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((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_get_pp_num_states(adev, data) \
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((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
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#define amdgpu_dpm_get_pp_table(adev, table) \
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((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
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#define amdgpu_dpm_set_pp_table(adev, buf, size) \
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((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))
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#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
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((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))
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#define amdgpu_dpm_force_clock_level(adev, type, level) \
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((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))
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#define amdgpu_dpm_get_sclk_od(adev) \
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((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_set_sclk_od(adev, value) \
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((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
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#define amdgpu_dpm_get_mclk_od(adev) \
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((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_set_mclk_od(adev, value) \
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((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
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#define amdgpu_dpm_dispatch_task(adev, task_id, input, output) \
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((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (input), (output))
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#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
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((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
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#define amdgpu_dpm_get_vce_clock_state(adev, i) \
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((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))
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#define amdgpu_dpm_get_performance_level(adev) \
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((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))
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#define amdgpu_dpm_reset_power_profile_state(adev, request) \
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((adev)->powerplay.pp_funcs->reset_power_profile_state(\
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(adev)->powerplay.pp_handle, request))
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#define amdgpu_dpm_get_power_profile_state(adev, query) \
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((adev)->powerplay.pp_funcs->get_power_profile_state(\
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(adev)->powerplay.pp_handle, query))
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#define amdgpu_dpm_set_power_profile_state(adev, request) \
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((adev)->powerplay.pp_funcs->set_power_profile_state(\
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(adev)->powerplay.pp_handle, request))
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#define amdgpu_dpm_switch_power_profile(adev, type) \
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((adev)->powerplay.pp_funcs->switch_power_profile(\
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(adev)->powerplay.pp_handle, type))
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#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \
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((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
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(adev)->powerplay.pp_handle, msg_id))
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struct amdgpu_dpm {
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struct amdgpu_ps *ps;
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/* number of valid power states */
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int num_ps;
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/* current power state that is active */
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struct amdgpu_ps *current_ps;
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/* requested power state */
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struct amdgpu_ps *requested_ps;
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/* boot up power state */
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struct amdgpu_ps *boot_ps;
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/* default uvd power state */
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struct amdgpu_ps *uvd_ps;
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/* vce requirements */
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u32 num_of_vce_states;
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struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
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enum amd_vce_level vce_level;
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enum amd_pm_state_type state;
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enum amd_pm_state_type user_state;
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enum amd_pm_state_type last_state;
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enum amd_pm_state_type last_user_state;
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u32 platform_caps;
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u32 voltage_response_time;
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u32 backbias_response_time;
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void *priv;
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u32 new_active_crtcs;
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int new_active_crtc_count;
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u32 current_active_crtcs;
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int current_active_crtc_count;
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struct amdgpu_dpm_dynamic_state dyn_state;
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struct amdgpu_dpm_fan fan;
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u32 tdp_limit;
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u32 near_tdp_limit;
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u32 near_tdp_limit_adjusted;
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u32 sq_ramping_threshold;
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u32 cac_leakage;
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u16 tdp_od_limit;
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u32 tdp_adjustment;
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u16 load_line_slope;
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bool power_control;
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bool ac_power;
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/* special states active */
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bool thermal_active;
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bool uvd_active;
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bool vce_active;
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/* thermal handling */
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struct amdgpu_dpm_thermal thermal;
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/* forced levels */
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enum amd_dpm_forced_level forced_level;
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};
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struct amdgpu_pm {
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struct mutex mutex;
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u32 current_sclk;
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u32 current_mclk;
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u32 default_sclk;
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u32 default_mclk;
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struct amdgpu_i2c_chan *i2c_bus;
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/* internal thermal controller on rv6xx+ */
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enum amdgpu_int_thermal_type int_thermal_type;
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struct device *int_hwmon_dev;
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/* fan control parameters */
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bool no_fan;
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u8 fan_pulses_per_revolution;
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u8 fan_min_rpm;
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u8 fan_max_rpm;
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/* dpm */
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bool dpm_enabled;
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bool sysfs_initialized;
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struct amdgpu_dpm dpm;
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const struct firmware *fw; /* SMC firmware */
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uint32_t fw_version;
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uint32_t pcie_gen_mask;
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uint32_t pcie_mlw_mask;
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struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
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};
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#define R600_SSTU_DFLT 0
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#define R600_SST_DFLT 0x00C8
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/* XXX are these ok? */
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#define R600_TEMP_RANGE_MIN (90 * 1000)
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#define R600_TEMP_RANGE_MAX (120 * 1000)
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#define FDO_PWM_MODE_STATIC 1
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#define FDO_PWM_MODE_STATIC_RPM 5
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enum amdgpu_td {
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AMDGPU_TD_AUTO,
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AMDGPU_TD_UP,
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AMDGPU_TD_DOWN,
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};
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enum amdgpu_display_watermark {
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AMDGPU_DISPLAY_WATERMARK_LOW = 0,
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AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
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};
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|
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enum amdgpu_display_gap
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|
{
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|
AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
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AMDGPU_PM_DISPLAY_GAP_VBLANK = 1,
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AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2,
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|
AMDGPU_PM_DISPLAY_GAP_IGNORE = 3,
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|
};
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|
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void amdgpu_dpm_print_class_info(u32 class, u32 class2);
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void amdgpu_dpm_print_cap_info(u32 caps);
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|
void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
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|
struct amdgpu_ps *rps);
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|
u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
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|
u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
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|
bool amdgpu_is_uvd_state(u32 class, u32 class2);
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|
void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
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|
u32 *p, u32 *u);
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|
int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
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|
|
|
bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
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|
|
|
int amdgpu_get_platform_caps(struct amdgpu_device *adev);
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|
|
|
int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
|
|
void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
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|
|
|
void amdgpu_add_thermal_controller(struct amdgpu_device *adev);
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|
|
|
enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
|
|
u32 sys_mask,
|
|
enum amdgpu_pcie_gen asic_gen,
|
|
enum amdgpu_pcie_gen default_gen);
|
|
|
|
u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
|
|
u16 asic_lanes,
|
|
u16 default_lanes);
|
|
u8 amdgpu_encode_pci_lane_width(u32 lanes);
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|
|
|
struct amd_vce_state*
|
|
amdgpu_get_vce_clock_state(void *handle, u32 idx);
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|
|
|
#endif
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