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![Monk Liu](/assets/img/avatar_default.png)
for SR-IOV, we must keep the pipeline-sync in the protection of COND_EXEC, otherwise the command consumed by CPG is not consistent when world switch triggerd, e.g.: world switch hit and the IB frame is skipped so the fence won't signal, thus CP will jump to the next DMAframe's pipeline-sync command, and it will make CP hang foever. after pipelin-sync moved into COND_EXEC the consistency can be guaranteed Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
382 lines
9.8 KiB
C
382 lines
9.8 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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* Christian König
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*/
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "atom.h"
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#define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000)
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/*
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* IB
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* IBs (Indirect Buffers) and areas of GPU accessible memory where
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* commands are stored. You can put a pointer to the IB in the
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* command ring and the hw will fetch the commands from the IB
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* and execute them. Generally userspace acceleration drivers
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* produce command buffers which are send to the kernel and
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* put in IBs for execution by the requested ring.
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*/
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static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
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/**
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* amdgpu_ib_get - request an IB (Indirect Buffer)
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*
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* @ring: ring index the IB is associated with
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* @size: requested IB size
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* @ib: IB object returned
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*
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* Request an IB (all asics). IBs are allocated using the
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* suballocator.
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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unsigned size, struct amdgpu_ib *ib)
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{
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int r;
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if (size) {
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r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
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&ib->sa_bo, size, 256);
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if (r) {
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dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
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return r;
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}
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ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
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if (!vm)
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ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
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}
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return 0;
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}
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/**
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* amdgpu_ib_free - free an IB (Indirect Buffer)
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*
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* @adev: amdgpu_device pointer
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* @ib: IB object to free
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* @f: the fence SA bo need wait on for the ib alloation
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*
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* Free an IB (all asics).
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*/
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void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
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struct dma_fence *f)
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{
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amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
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}
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/**
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* amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
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*
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* @adev: amdgpu_device pointer
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* @num_ibs: number of IBs to schedule
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* @ibs: IB objects to schedule
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* @f: fence created during this submission
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*
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* Schedule an IB on the associated ring (all asics).
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* Returns 0 on success, error on failure.
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*
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* On SI, there are two parallel engines fed from the primary ring,
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* the CE (Constant Engine) and the DE (Drawing Engine). Since
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* resource descriptors have moved to memory, the CE allows you to
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* prime the caches while the DE is updating register state so that
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* the resource descriptors will be already in cache when the draw is
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* processed. To accomplish this, the userspace driver submits two
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* IBs, one for the CE and one for the DE. If there is a CE IB (called
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* a CONST_IB), it will be put on the ring prior to the DE IB. Prior
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* to SI there was just a DE IB.
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*/
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int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
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struct amdgpu_ib *ibs, struct amdgpu_job *job,
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struct dma_fence **f)
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_ib *ib = &ibs[0];
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struct dma_fence *tmp = NULL;
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bool skip_preamble, need_ctx_switch;
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unsigned patch_offset = ~0;
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struct amdgpu_vm *vm;
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uint64_t fence_ctx;
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uint32_t status = 0, alloc_size;
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unsigned i;
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int r = 0;
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bool need_pipe_sync = false;
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if (num_ibs == 0)
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return -EINVAL;
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/* ring tests don't use a job */
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if (job) {
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vm = job->vm;
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fence_ctx = job->fence_ctx;
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} else {
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vm = NULL;
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fence_ctx = 0;
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}
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if (!ring->ready) {
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dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
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return -EINVAL;
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}
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if (vm && !job->vm_id) {
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dev_err(adev->dev, "VM IB without ID\n");
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return -EINVAL;
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}
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alloc_size = ring->funcs->emit_frame_size + num_ibs *
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ring->funcs->emit_ib_size;
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r = amdgpu_ring_alloc(ring, alloc_size);
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if (r) {
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dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
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return r;
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}
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if (ring->funcs->emit_pipeline_sync && job &&
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((tmp = amdgpu_sync_get_fence(&job->sched_sync)) ||
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amdgpu_vm_need_pipeline_sync(ring, job))) {
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need_pipe_sync = true;
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dma_fence_put(tmp);
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}
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if (ring->funcs->insert_start)
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ring->funcs->insert_start(ring);
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if (job) {
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r = amdgpu_vm_flush(ring, job, need_pipe_sync);
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if (r) {
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amdgpu_ring_undo(ring);
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return r;
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}
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}
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if (ring->funcs->init_cond_exec)
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patch_offset = amdgpu_ring_init_cond_exec(ring);
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if (ring->funcs->emit_hdp_flush
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#ifdef CONFIG_X86_64
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&& !(adev->flags & AMD_IS_APU)
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#endif
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)
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amdgpu_ring_emit_hdp_flush(ring);
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skip_preamble = ring->current_ctx == fence_ctx;
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need_ctx_switch = ring->current_ctx != fence_ctx;
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if (job && ring->funcs->emit_cntxcntl) {
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if (need_ctx_switch)
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status |= AMDGPU_HAVE_CTX_SWITCH;
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status |= job->preamble_status;
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amdgpu_ring_emit_cntxcntl(ring, status);
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}
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for (i = 0; i < num_ibs; ++i) {
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ib = &ibs[i];
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/* drop preamble IBs if we don't have a context switch */
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if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
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skip_preamble &&
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!(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) &&
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!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
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continue;
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amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
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need_ctx_switch);
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need_ctx_switch = false;
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}
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if (ring->funcs->emit_tmz)
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amdgpu_ring_emit_tmz(ring, false);
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if (ring->funcs->emit_hdp_invalidate
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#ifdef CONFIG_X86_64
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&& !(adev->flags & AMD_IS_APU)
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#endif
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)
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amdgpu_ring_emit_hdp_invalidate(ring);
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r = amdgpu_fence_emit(ring, f);
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if (r) {
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dev_err(adev->dev, "failed to emit fence (%d)\n", r);
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if (job && job->vm_id)
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amdgpu_vm_reset_id(adev, ring->funcs->vmhub,
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job->vm_id);
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amdgpu_ring_undo(ring);
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return r;
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}
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if (ring->funcs->insert_end)
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ring->funcs->insert_end(ring);
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/* wrap the last IB with fence */
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if (job && job->uf_addr) {
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amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence,
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AMDGPU_FENCE_FLAG_64BIT);
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}
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if (patch_offset != ~0 && ring->funcs->patch_cond_exec)
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amdgpu_ring_patch_cond_exec(ring, patch_offset);
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ring->current_ctx = fence_ctx;
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if (vm && ring->funcs->emit_switch_buffer)
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amdgpu_ring_emit_switch_buffer(ring);
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amdgpu_ring_commit(ring);
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return 0;
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}
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/**
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* amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
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*
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* @adev: amdgpu_device pointer
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*
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* Initialize the suballocator to manage a pool of memory
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* for use as IBs (all asics).
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_ib_pool_init(struct amdgpu_device *adev)
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{
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int r;
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if (adev->ib_pool_ready) {
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return 0;
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}
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r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
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AMDGPU_IB_POOL_SIZE*64*1024,
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AMDGPU_GPU_PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_GTT);
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if (r) {
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return r;
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}
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r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo);
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if (r) {
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return r;
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}
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adev->ib_pool_ready = true;
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if (amdgpu_debugfs_sa_init(adev)) {
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dev_err(adev->dev, "failed to register debugfs file for SA\n");
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}
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return 0;
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}
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/**
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* amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
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*
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* @adev: amdgpu_device pointer
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*
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* Tear down the suballocator managing the pool of memory
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* for use as IBs (all asics).
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*/
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void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
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{
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if (adev->ib_pool_ready) {
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amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo);
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amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
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adev->ib_pool_ready = false;
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}
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}
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/**
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* amdgpu_ib_ring_tests - test IBs on the rings
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*
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* @adev: amdgpu_device pointer
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*
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* Test an IB (Indirect Buffer) on each ring.
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* If the test fails, disable the ring.
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* Returns 0 on success, error if the primary GFX ring
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* IB test fails.
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*/
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int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
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{
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unsigned i;
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int r, ret = 0;
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
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struct amdgpu_ring *ring = adev->rings[i];
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if (!ring || !ring->ready)
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continue;
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r = amdgpu_ring_test_ib(ring, AMDGPU_IB_TEST_TIMEOUT);
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if (r) {
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ring->ready = false;
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if (ring == &adev->gfx.gfx_ring[0]) {
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/* oh, oh, that's really bad */
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DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
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adev->accel_working = false;
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return r;
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} else {
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/* still not good, but we can live with it */
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DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
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ret = r;
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}
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}
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}
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return ret;
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct amdgpu_device *adev = dev->dev_private;
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amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
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return 0;
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}
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static const struct drm_info_list amdgpu_debugfs_sa_list[] = {
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{"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
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};
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#endif
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static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
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#else
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return 0;
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#endif
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}
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