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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Evan Quan](/assets/img/avatar_default.png)
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
902 lines
23 KiB
C
902 lines
23 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include "amdgpu.h"
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#include "gmc_v9_0.h"
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#include "amdgpu_atomfirmware.h"
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#include "vega10/soc15ip.h"
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#include "vega10/HDP/hdp_4_0_offset.h"
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#include "vega10/HDP/hdp_4_0_sh_mask.h"
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#include "vega10/GC/gc_9_0_sh_mask.h"
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#include "vega10/DC/dce_12_0_offset.h"
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#include "vega10/DC/dce_12_0_sh_mask.h"
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#include "vega10/vega10_enum.h"
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#include "vega10/MMHUB/mmhub_1_0_offset.h"
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#include "vega10/ATHUB/athub_1_0_offset.h"
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#include "soc15_common.h"
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#include "nbio_v6_1.h"
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#include "nbio_v7_0.h"
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#include "gfxhub_v1_0.h"
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#include "mmhub_v1_0.h"
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#define mmDF_CS_AON0_DramBaseAddress0 0x0044
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#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
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//DF_CS_AON0_DramBaseAddress0
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#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
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#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
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#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
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#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
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#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
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#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
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#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
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#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
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#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
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#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
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/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
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#define AMDGPU_NUM_OF_VMIDS 8
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static const u32 golden_settings_vega10_hdp[] =
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{
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0xf64, 0x0fffffff, 0x00000000,
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0xf65, 0x0fffffff, 0x00000000,
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0xf66, 0x0fffffff, 0x00000000,
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0xf67, 0x0fffffff, 0x00000000,
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0xf68, 0x0fffffff, 0x00000000,
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0xf6a, 0x0fffffff, 0x00000000,
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0xf6b, 0x0fffffff, 0x00000000,
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0xf6c, 0x0fffffff, 0x00000000,
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0xf6d, 0x0fffffff, 0x00000000,
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0xf6e, 0x0fffffff, 0x00000000,
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};
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static const u32 golden_settings_mmhub_1_0_0[] =
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{
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SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
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SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
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};
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static const u32 golden_settings_athub_1_0_0[] =
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{
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SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
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SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
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};
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static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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struct amdgpu_vmhub *hub;
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u32 tmp, reg, bits, i, j;
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bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
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VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
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VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
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VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
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VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
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VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
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VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
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switch (state) {
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case AMDGPU_IRQ_STATE_DISABLE:
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for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
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hub = &adev->vmhub[j];
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for (i = 0; i < 16; i++) {
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reg = hub->vm_context0_cntl + i;
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tmp = RREG32(reg);
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tmp &= ~bits;
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WREG32(reg, tmp);
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}
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}
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break;
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case AMDGPU_IRQ_STATE_ENABLE:
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for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
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hub = &adev->vmhub[j];
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for (i = 0; i < 16; i++) {
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reg = hub->vm_context0_cntl + i;
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tmp = RREG32(reg);
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tmp |= bits;
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WREG32(reg, tmp);
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}
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}
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default:
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break;
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}
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return 0;
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}
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static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
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uint32_t status = 0;
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u64 addr;
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addr = (u64)entry->src_data[0] << 12;
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addr |= ((u64)entry->src_data[1] & 0xf) << 44;
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if (!amdgpu_sriov_vf(adev)) {
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status = RREG32(hub->vm_l2_pro_fault_status);
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WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
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}
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if (printk_ratelimit()) {
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dev_err(adev->dev,
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"[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n",
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entry->vm_id_src ? "mmhub" : "gfxhub",
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entry->src_id, entry->ring_id, entry->vm_id,
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entry->pas_id);
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dev_err(adev->dev, " at page 0x%016llx from %d\n",
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addr, entry->client_id);
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if (!amdgpu_sriov_vf(adev))
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dev_err(adev->dev,
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"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
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status);
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}
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return 0;
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}
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static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
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.set = gmc_v9_0_vm_fault_interrupt_state,
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.process = gmc_v9_0_process_interrupt,
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};
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static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
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{
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adev->mc.vm_fault.num_types = 1;
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adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
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}
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static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
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{
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u32 req = 0;
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/* invalidate using legacy mode on vm_id*/
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req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
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PER_VMID_INVALIDATE_REQ, 1 << vm_id);
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req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
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req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
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req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
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req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
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req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
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req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
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req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
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CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
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return req;
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}
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/*
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* GART
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* VMID 0 is the physical GPU addresses as used by the kernel.
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* VMIDs 1-15 are used for userspace clients and are handled
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* by the amdgpu vm/hsa code.
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*/
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/**
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* gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
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*
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* @adev: amdgpu_device pointer
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* @vmid: vm instance to flush
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*
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* Flush the TLB for the requested page table.
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*/
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static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
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uint32_t vmid)
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{
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/* Use register 17 for GART */
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const unsigned eng = 17;
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unsigned i, j;
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/* flush hdp cache */
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if (adev->flags & AMD_IS_APU)
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nbio_v7_0_hdp_flush(adev);
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else
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nbio_v6_1_hdp_flush(adev);
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spin_lock(&adev->mc.invalidate_lock);
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for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
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struct amdgpu_vmhub *hub = &adev->vmhub[i];
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u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
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WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
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/* Busy wait for ACK.*/
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for (j = 0; j < 100; j++) {
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tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
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tmp &= 1 << vmid;
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if (tmp)
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break;
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cpu_relax();
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}
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if (j < 100)
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continue;
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/* Wait for ACK with a delay.*/
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for (j = 0; j < adev->usec_timeout; j++) {
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tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
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tmp &= 1 << vmid;
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if (tmp)
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break;
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udelay(1);
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}
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if (j < adev->usec_timeout)
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continue;
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DRM_ERROR("Timeout waiting for VM flush ACK!\n");
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}
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spin_unlock(&adev->mc.invalidate_lock);
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}
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/**
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* gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
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*
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* @adev: amdgpu_device pointer
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* @cpu_pt_addr: cpu address of the page table
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* @gpu_page_idx: entry in the page table to update
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* @addr: dst addr to write into pte/pde
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* @flags: access flags
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*
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* Update the page tables using the CPU.
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*/
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static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
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void *cpu_pt_addr,
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uint32_t gpu_page_idx,
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uint64_t addr,
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uint64_t flags)
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{
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void __iomem *ptr = (void *)cpu_pt_addr;
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uint64_t value;
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/*
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* PTE format on VEGA 10:
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* 63:59 reserved
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* 58:57 mtype
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* 56 F
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* 55 L
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* 54 P
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* 53 SW
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* 52 T
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* 50:48 reserved
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* 47:12 4k physical page base address
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* 11:7 fragment
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* 6 write
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* 5 read
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* 4 exe
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* 3 Z
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* 2 snooped
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* 1 system
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* 0 valid
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*
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* PDE format on VEGA 10:
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* 63:59 block fragment size
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* 58:55 reserved
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* 54 P
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* 53:48 reserved
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* 47:6 physical base address of PD or PTE
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* 5:3 reserved
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* 2 C
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* 1 system
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* 0 valid
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*/
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/*
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* The following is for PTE only. GART does not have PDEs.
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*/
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value = addr & 0x0000FFFFFFFFF000ULL;
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value |= flags;
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writeq(value, ptr + (gpu_page_idx * 8));
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return 0;
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}
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static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
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uint32_t flags)
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{
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uint64_t pte_flag = 0;
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if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
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pte_flag |= AMDGPU_PTE_EXECUTABLE;
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if (flags & AMDGPU_VM_PAGE_READABLE)
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pte_flag |= AMDGPU_PTE_READABLE;
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if (flags & AMDGPU_VM_PAGE_WRITEABLE)
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pte_flag |= AMDGPU_PTE_WRITEABLE;
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switch (flags & AMDGPU_VM_MTYPE_MASK) {
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case AMDGPU_VM_MTYPE_DEFAULT:
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pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
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break;
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case AMDGPU_VM_MTYPE_NC:
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pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
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break;
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case AMDGPU_VM_MTYPE_WC:
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pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
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break;
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case AMDGPU_VM_MTYPE_CC:
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pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
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break;
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case AMDGPU_VM_MTYPE_UC:
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pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
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break;
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default:
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pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
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break;
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}
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if (flags & AMDGPU_VM_PAGE_PRT)
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pte_flag |= AMDGPU_PTE_PRT;
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return pte_flag;
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}
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static u64 gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, u64 addr)
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{
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addr = adev->vm_manager.vram_base_offset + addr - adev->mc.vram_start;
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BUG_ON(addr & 0xFFFF00000000003FULL);
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return addr;
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}
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static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
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.flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
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.set_pte_pde = gmc_v9_0_gart_set_pte_pde,
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.get_invalidate_req = gmc_v9_0_get_invalidate_req,
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.get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
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.get_vm_pde = gmc_v9_0_get_vm_pde
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};
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static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
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{
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if (adev->gart.gart_funcs == NULL)
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adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
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}
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static int gmc_v9_0_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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gmc_v9_0_set_gart_funcs(adev);
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gmc_v9_0_set_irq_funcs(adev);
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return 0;
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}
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static int gmc_v9_0_late_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 };
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unsigned i;
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for(i = 0; i < adev->num_rings; ++i) {
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struct amdgpu_ring *ring = adev->rings[i];
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unsigned vmhub = ring->funcs->vmhub;
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ring->vm_inv_eng = vm_inv_eng[vmhub]++;
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dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
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ring->idx, ring->name, ring->vm_inv_eng,
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ring->funcs->vmhub);
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}
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/* Engine 17 is used for GART flushes */
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for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
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BUG_ON(vm_inv_eng[i] > 17);
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return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
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}
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static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
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struct amdgpu_mc *mc)
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{
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u64 base = 0;
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if (!amdgpu_sriov_vf(adev))
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base = mmhub_v1_0_get_fb_location(adev);
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amdgpu_vram_location(adev, &adev->mc, base);
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amdgpu_gart_location(adev, mc);
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/* base offset of vram pages */
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if (adev->flags & AMD_IS_APU)
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adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
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else
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adev->vm_manager.vram_base_offset = 0;
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}
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/**
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* gmc_v9_0_mc_init - initialize the memory controller driver params
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*
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* @adev: amdgpu_device pointer
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*
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* Look up the amount of vram, vram width, and decide how to place
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* vram and gart within the GPU's physical address space.
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* Returns 0 for success.
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*/
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static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
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|
{
|
|
u32 tmp;
|
|
int chansize, numchan;
|
|
|
|
adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
|
|
if (!adev->mc.vram_width) {
|
|
/* hbm memory channel size */
|
|
chansize = 128;
|
|
|
|
tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
|
|
tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
|
|
tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
|
|
switch (tmp) {
|
|
case 0:
|
|
default:
|
|
numchan = 1;
|
|
break;
|
|
case 1:
|
|
numchan = 2;
|
|
break;
|
|
case 2:
|
|
numchan = 0;
|
|
break;
|
|
case 3:
|
|
numchan = 4;
|
|
break;
|
|
case 4:
|
|
numchan = 0;
|
|
break;
|
|
case 5:
|
|
numchan = 8;
|
|
break;
|
|
case 6:
|
|
numchan = 0;
|
|
break;
|
|
case 7:
|
|
numchan = 16;
|
|
break;
|
|
case 8:
|
|
numchan = 2;
|
|
break;
|
|
}
|
|
adev->mc.vram_width = numchan * chansize;
|
|
}
|
|
|
|
/* Could aper size report 0 ? */
|
|
adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
|
|
adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
|
|
/* size in MB on si */
|
|
adev->mc.mc_vram_size =
|
|
((adev->flags & AMD_IS_APU) ? nbio_v7_0_get_memsize(adev) :
|
|
nbio_v6_1_get_memsize(adev)) * 1024ULL * 1024ULL;
|
|
adev->mc.real_vram_size = adev->mc.mc_vram_size;
|
|
adev->mc.visible_vram_size = adev->mc.aper_size;
|
|
|
|
/* In case the PCI BAR is larger than the actual amount of vram */
|
|
if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
|
|
adev->mc.visible_vram_size = adev->mc.real_vram_size;
|
|
|
|
/* set the gart size */
|
|
if (amdgpu_gart_size == -1) {
|
|
switch (adev->asic_type) {
|
|
case CHIP_VEGA10: /* all engines support GPUVM */
|
|
default:
|
|
adev->mc.gart_size = 256ULL << 20;
|
|
break;
|
|
case CHIP_RAVEN: /* DCE SG support */
|
|
adev->mc.gart_size = 1024ULL << 20;
|
|
break;
|
|
}
|
|
} else {
|
|
adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
|
|
}
|
|
|
|
gmc_v9_0_vram_gtt_location(adev, &adev->mc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
|
|
{
|
|
int r;
|
|
|
|
if (adev->gart.robj) {
|
|
WARN(1, "VEGA10 PCIE GART already initialized\n");
|
|
return 0;
|
|
}
|
|
/* Initialize common gart structure */
|
|
r = amdgpu_gart_init(adev);
|
|
if (r)
|
|
return r;
|
|
adev->gart.table_size = adev->gart.num_gpu_pages * 8;
|
|
adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
|
|
AMDGPU_PTE_EXECUTABLE;
|
|
return amdgpu_gart_table_vram_alloc(adev);
|
|
}
|
|
|
|
static int gmc_v9_0_sw_init(void *handle)
|
|
{
|
|
int r;
|
|
int dma_bits;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
gfxhub_v1_0_init(adev);
|
|
mmhub_v1_0_init(adev);
|
|
|
|
spin_lock_init(&adev->mc.invalidate_lock);
|
|
|
|
switch (adev->asic_type) {
|
|
case CHIP_RAVEN:
|
|
adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
|
|
if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
|
|
adev->vm_manager.vm_size = 1U << 18;
|
|
adev->vm_manager.block_size = 9;
|
|
adev->vm_manager.num_level = 3;
|
|
amdgpu_vm_set_fragment_size(adev, 9);
|
|
} else {
|
|
/* vm_size is 64GB for legacy 2-level page support */
|
|
amdgpu_vm_adjust_size(adev, 64, 9);
|
|
adev->vm_manager.num_level = 1;
|
|
}
|
|
break;
|
|
case CHIP_VEGA10:
|
|
/* XXX Don't know how to get VRAM type yet. */
|
|
adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
|
|
/*
|
|
* To fulfill 4-level page support,
|
|
* vm size is 256TB (48bit), maximum size of Vega10,
|
|
* block size 512 (9bit)
|
|
*/
|
|
adev->vm_manager.vm_size = 1U << 18;
|
|
adev->vm_manager.block_size = 9;
|
|
adev->vm_manager.num_level = 3;
|
|
amdgpu_vm_set_fragment_size(adev, 9);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
|
|
adev->vm_manager.vm_size,
|
|
adev->vm_manager.block_size,
|
|
adev->vm_manager.fragment_size);
|
|
|
|
/* This interrupt is VMC page fault.*/
|
|
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
|
|
&adev->mc.vm_fault);
|
|
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
|
|
&adev->mc.vm_fault);
|
|
|
|
if (r)
|
|
return r;
|
|
|
|
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
|
|
|
|
/* Set the internal MC address mask
|
|
* This is the max address of the GPU's
|
|
* internal address space.
|
|
*/
|
|
adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
|
|
|
|
/*
|
|
* It needs to reserve 8M stolen memory for vega10
|
|
* TODO: Figure out how to avoid that...
|
|
*/
|
|
adev->mc.stolen_size = 8 * 1024 * 1024;
|
|
|
|
/* set DMA mask + need_dma32 flags.
|
|
* PCIE - can handle 44-bits.
|
|
* IGP - can handle 44-bits
|
|
* PCI - dma32 for legacy pci gart, 44 bits on vega10
|
|
*/
|
|
adev->need_dma32 = false;
|
|
dma_bits = adev->need_dma32 ? 32 : 44;
|
|
r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
|
|
if (r) {
|
|
adev->need_dma32 = true;
|
|
dma_bits = 32;
|
|
printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
|
|
}
|
|
r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
|
|
if (r) {
|
|
pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
|
|
printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
|
|
}
|
|
|
|
r = gmc_v9_0_mc_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
/* Memory manager */
|
|
r = amdgpu_bo_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
r = gmc_v9_0_gart_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
/*
|
|
* number of VMs
|
|
* VMID 0 is reserved for System
|
|
* amdgpu graphics/compute will use VMIDs 1-7
|
|
* amdkfd will use VMIDs 8-15
|
|
*/
|
|
adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
|
|
adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
|
|
|
|
amdgpu_vm_manager_init(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* gmc_v8_0_gart_fini - vm fini callback
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
*
|
|
* Tears down the driver GART/VM setup (CIK).
|
|
*/
|
|
static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
|
|
{
|
|
amdgpu_gart_table_vram_free(adev);
|
|
amdgpu_gart_fini(adev);
|
|
}
|
|
|
|
static int gmc_v9_0_sw_fini(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
amdgpu_vm_manager_fini(adev);
|
|
gmc_v9_0_gart_fini(adev);
|
|
amdgpu_gem_force_release(adev);
|
|
amdgpu_bo_fini(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
|
|
{
|
|
switch (adev->asic_type) {
|
|
case CHIP_VEGA10:
|
|
amdgpu_program_register_sequence(adev,
|
|
golden_settings_mmhub_1_0_0,
|
|
(const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
|
|
amdgpu_program_register_sequence(adev,
|
|
golden_settings_athub_1_0_0,
|
|
(const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
|
|
break;
|
|
case CHIP_RAVEN:
|
|
amdgpu_program_register_sequence(adev,
|
|
golden_settings_athub_1_0_0,
|
|
(const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* gmc_v9_0_gart_enable - gart enable
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
*/
|
|
static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
|
|
{
|
|
int r;
|
|
bool value;
|
|
u32 tmp;
|
|
|
|
amdgpu_program_register_sequence(adev,
|
|
golden_settings_vega10_hdp,
|
|
(const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
|
|
|
|
if (adev->gart.robj == NULL) {
|
|
dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
|
|
return -EINVAL;
|
|
}
|
|
r = amdgpu_gart_table_vram_pin(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
switch (adev->asic_type) {
|
|
case CHIP_RAVEN:
|
|
mmhub_v1_0_initialize_power_gating(adev);
|
|
mmhub_v1_0_update_power_gating(adev, true);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
r = gfxhub_v1_0_gart_enable(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
r = mmhub_v1_0_gart_enable(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
|
|
|
|
tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
|
|
WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
|
|
|
|
/* After HDP is initialized, flush HDP.*/
|
|
if (adev->flags & AMD_IS_APU)
|
|
nbio_v7_0_hdp_flush(adev);
|
|
else
|
|
nbio_v6_1_hdp_flush(adev);
|
|
|
|
if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
|
|
value = false;
|
|
else
|
|
value = true;
|
|
|
|
gfxhub_v1_0_set_fault_enable_default(adev, value);
|
|
mmhub_v1_0_set_fault_enable_default(adev, value);
|
|
gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
|
|
|
|
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
|
|
(unsigned)(adev->mc.gart_size >> 20),
|
|
(unsigned long long)adev->gart.table_addr);
|
|
adev->gart.ready = true;
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v9_0_hw_init(void *handle)
|
|
{
|
|
int r;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
/* The sequence of these two function calls matters.*/
|
|
gmc_v9_0_init_golden_registers(adev);
|
|
|
|
if (adev->mode_info.num_crtc) {
|
|
/* Lockout access through VGA aperture*/
|
|
WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
|
|
|
|
/* disable VGA render */
|
|
WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
|
|
}
|
|
|
|
r = gmc_v9_0_gart_enable(adev);
|
|
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* gmc_v9_0_gart_disable - gart disable
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
*
|
|
* This disables all VM page table.
|
|
*/
|
|
static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
|
|
{
|
|
gfxhub_v1_0_gart_disable(adev);
|
|
mmhub_v1_0_gart_disable(adev);
|
|
amdgpu_gart_table_vram_unpin(adev);
|
|
}
|
|
|
|
static int gmc_v9_0_hw_fini(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
if (amdgpu_sriov_vf(adev)) {
|
|
/* full access mode, so don't touch any GMC register */
|
|
DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
|
|
return 0;
|
|
}
|
|
|
|
amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
|
|
gmc_v9_0_gart_disable(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v9_0_suspend(void *handle)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
return gmc_v9_0_hw_fini(adev);
|
|
}
|
|
|
|
static int gmc_v9_0_resume(void *handle)
|
|
{
|
|
int r;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
r = gmc_v9_0_hw_init(adev);
|
|
if (r)
|
|
return r;
|
|
|
|
amdgpu_vm_reset_all_ids(adev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool gmc_v9_0_is_idle(void *handle)
|
|
{
|
|
/* MC is always ready in GMC v9.*/
|
|
return true;
|
|
}
|
|
|
|
static int gmc_v9_0_wait_for_idle(void *handle)
|
|
{
|
|
/* There is no need to wait for MC idle in GMC v9.*/
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v9_0_soft_reset(void *handle)
|
|
{
|
|
/* XXX for emulation.*/
|
|
return 0;
|
|
}
|
|
|
|
static int gmc_v9_0_set_clockgating_state(void *handle,
|
|
enum amd_clockgating_state state)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
return mmhub_v1_0_set_clockgating(adev, state);
|
|
}
|
|
|
|
static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
|
|
{
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
mmhub_v1_0_get_clockgating(adev, flags);
|
|
}
|
|
|
|
static int gmc_v9_0_set_powergating_state(void *handle,
|
|
enum amd_powergating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
|
|
.name = "gmc_v9_0",
|
|
.early_init = gmc_v9_0_early_init,
|
|
.late_init = gmc_v9_0_late_init,
|
|
.sw_init = gmc_v9_0_sw_init,
|
|
.sw_fini = gmc_v9_0_sw_fini,
|
|
.hw_init = gmc_v9_0_hw_init,
|
|
.hw_fini = gmc_v9_0_hw_fini,
|
|
.suspend = gmc_v9_0_suspend,
|
|
.resume = gmc_v9_0_resume,
|
|
.is_idle = gmc_v9_0_is_idle,
|
|
.wait_for_idle = gmc_v9_0_wait_for_idle,
|
|
.soft_reset = gmc_v9_0_soft_reset,
|
|
.set_clockgating_state = gmc_v9_0_set_clockgating_state,
|
|
.set_powergating_state = gmc_v9_0_set_powergating_state,
|
|
.get_clockgating_state = gmc_v9_0_get_clockgating_state,
|
|
};
|
|
|
|
const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
|
|
{
|
|
.type = AMD_IP_BLOCK_TYPE_GMC,
|
|
.major = 9,
|
|
.minor = 0,
|
|
.rev = 0,
|
|
.funcs = &gmc_v9_0_ip_funcs,
|
|
};
|