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f2114795f7
Various muxes can aggregate multiple interrupts from each i2c bus. All of the muxes with interrupt support combine the active low irq lines using an internal 'and' function and generate a combined active low output. The muxes do provide the ability to read a control register to determine which irq is active. By making the mux an irq controller isr latency can potentially be reduced by reading the status register and then only calling the registered isr on that bus segment. As there is no irq masking on the mux irq are disabled until irq_unmask is called at least once. Signed-off-by: Phil Reid <preid@electromag.com.au> Signed-off-by: Peter Rosin <peda@axentia.se> |
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| .. | ||
| i2c-arb-gpio-challenge.c | ||
| i2c-demux-pinctrl.c | ||
| i2c-mux-gpio.c | ||
| i2c-mux-mlxcpld.c | ||
| i2c-mux-pca954x.c | ||
| i2c-mux-pca9541.c | ||
| i2c-mux-pinctrl.c | ||
| i2c-mux-reg.c | ||
| Kconfig | ||
| Makefile | ||