Jordan Crouse f56d9df656 drm/msm/adreno: Read the speed bins for a5xx targets ... Some 5xx based chipsets have different bins for GPU clock speeds. Read the fuses (if applicable) and set the appropriate OPP table. This will only work with OPP v2 tables - the bin will be ignored for legacy pwrlevel tables. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>		2018-01-10 08:58:42 -05:00
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drm	drm/msm/adreno: Read the speed bins for a5xx targets	2018-01-10 08:58:42 -05:00
host1x	main drm pull request for v4.15	2017-11-15 20:42:10 -08:00
ipu-v3	fixes/cleanups for rc1, non-desktop flags for VR	2017-11-23 21:04:56 -10:00
vga	vgaarb: Factor out EFI and fallback default device selection	2017-10-18 10:04:56 +02:00
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