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![Yu Chen](/assets/img/avatar_default.png)
SPLIT_BOUNDARY_DISABLE should be set for DesignWare USB3 DRD Core of Hisilicon Kirin Soc when dwc3 core act as host. [mchehab: dropped a dev_dbg() as only traces are now allowwed on this driver] Signed-off-by: Yu Chen <chenyu56@huawei.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Felipe Balbi <balbi@kernel.org>
1962 lines
47 KiB
C
1962 lines
47 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/**
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* core.c - DesignWare USB3 DRD Controller Core file
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*/
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#include <linux/clk.h>
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#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/of.h>
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#include <linux/acpi.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/reset.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/of.h>
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#include <linux/usb/otg.h>
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#include "core.h"
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#include "gadget.h"
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#include "io.h"
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#include "debug.h"
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#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
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/**
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* dwc3_get_dr_mode - Validates and sets dr_mode
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* @dwc: pointer to our context structure
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*/
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static int dwc3_get_dr_mode(struct dwc3 *dwc)
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{
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enum usb_dr_mode mode;
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struct device *dev = dwc->dev;
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unsigned int hw_mode;
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if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
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dwc->dr_mode = USB_DR_MODE_OTG;
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mode = dwc->dr_mode;
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hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
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switch (hw_mode) {
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case DWC3_GHWPARAMS0_MODE_GADGET:
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if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
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dev_err(dev,
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"Controller does not support host mode.\n");
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return -EINVAL;
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}
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mode = USB_DR_MODE_PERIPHERAL;
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break;
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case DWC3_GHWPARAMS0_MODE_HOST:
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if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
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dev_err(dev,
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"Controller does not support device mode.\n");
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return -EINVAL;
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}
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mode = USB_DR_MODE_HOST;
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break;
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default:
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if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
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mode = USB_DR_MODE_HOST;
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else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
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mode = USB_DR_MODE_PERIPHERAL;
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/*
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* DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
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* mode. If the controller supports DRD but the dr_mode is not
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* specified or set to OTG, then set the mode to peripheral.
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*/
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if (mode == USB_DR_MODE_OTG &&
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(!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
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!device_property_read_bool(dwc->dev, "usb-role-switch")) &&
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!DWC3_VER_IS_PRIOR(DWC3, 330A))
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mode = USB_DR_MODE_PERIPHERAL;
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}
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if (mode != dwc->dr_mode) {
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dev_warn(dev,
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"Configuration mismatch. dr_mode forced to %s\n",
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mode == USB_DR_MODE_HOST ? "host" : "gadget");
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dwc->dr_mode = mode;
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}
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return 0;
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}
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void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
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{
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u32 reg;
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
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reg |= DWC3_GCTL_PRTCAPDIR(mode);
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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dwc->current_dr_role = mode;
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}
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static void __dwc3_set_mode(struct work_struct *work)
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{
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struct dwc3 *dwc = work_to_dwc(work);
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unsigned long flags;
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int ret;
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u32 reg;
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pm_runtime_get_sync(dwc->dev);
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if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
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dwc3_otg_update(dwc, 0);
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if (!dwc->desired_dr_role)
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goto out;
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if (dwc->desired_dr_role == dwc->current_dr_role)
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goto out;
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if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
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goto out;
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switch (dwc->current_dr_role) {
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case DWC3_GCTL_PRTCAP_HOST:
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dwc3_host_exit(dwc);
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break;
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case DWC3_GCTL_PRTCAP_DEVICE:
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dwc3_gadget_exit(dwc);
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dwc3_event_buffers_cleanup(dwc);
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break;
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case DWC3_GCTL_PRTCAP_OTG:
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dwc3_otg_exit(dwc);
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spin_lock_irqsave(&dwc->lock, flags);
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dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
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spin_unlock_irqrestore(&dwc->lock, flags);
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dwc3_otg_update(dwc, 1);
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break;
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default:
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break;
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}
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spin_lock_irqsave(&dwc->lock, flags);
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dwc3_set_prtcap(dwc, dwc->desired_dr_role);
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spin_unlock_irqrestore(&dwc->lock, flags);
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switch (dwc->desired_dr_role) {
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case DWC3_GCTL_PRTCAP_HOST:
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ret = dwc3_host_init(dwc);
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if (ret) {
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dev_err(dwc->dev, "failed to initialize host\n");
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} else {
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if (dwc->usb2_phy)
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otg_set_vbus(dwc->usb2_phy->otg, true);
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phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
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phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
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if (dwc->dis_split_quirk) {
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reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
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reg |= DWC3_GUCTL3_SPLITDISABLE;
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dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
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}
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}
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break;
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case DWC3_GCTL_PRTCAP_DEVICE:
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dwc3_event_buffers_setup(dwc);
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if (dwc->usb2_phy)
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otg_set_vbus(dwc->usb2_phy->otg, false);
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phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
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phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
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ret = dwc3_gadget_init(dwc);
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if (ret)
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dev_err(dwc->dev, "failed to initialize peripheral\n");
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break;
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case DWC3_GCTL_PRTCAP_OTG:
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dwc3_otg_init(dwc);
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dwc3_otg_update(dwc, 0);
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break;
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default:
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break;
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}
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out:
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pm_runtime_mark_last_busy(dwc->dev);
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pm_runtime_put_autosuspend(dwc->dev);
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}
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void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
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{
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unsigned long flags;
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if (dwc->dr_mode != USB_DR_MODE_OTG)
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return;
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spin_lock_irqsave(&dwc->lock, flags);
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dwc->desired_dr_role = mode;
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spin_unlock_irqrestore(&dwc->lock, flags);
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queue_work(system_freezable_wq, &dwc->drd_work);
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}
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u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
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{
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struct dwc3 *dwc = dep->dwc;
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u32 reg;
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dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
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DWC3_GDBGFIFOSPACE_NUM(dep->number) |
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DWC3_GDBGFIFOSPACE_TYPE(type));
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reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
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return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
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}
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/**
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* dwc3_core_soft_reset - Issues core soft reset and PHY reset
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* @dwc: pointer to our context structure
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*/
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static int dwc3_core_soft_reset(struct dwc3 *dwc)
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{
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u32 reg;
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int retries = 1000;
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int ret;
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usb_phy_init(dwc->usb2_phy);
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usb_phy_init(dwc->usb3_phy);
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ret = phy_init(dwc->usb2_generic_phy);
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if (ret < 0)
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return ret;
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ret = phy_init(dwc->usb3_generic_phy);
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if (ret < 0) {
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phy_exit(dwc->usb2_generic_phy);
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return ret;
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}
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/*
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* We're resetting only the device side because, if we're in host mode,
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* XHCI driver will reset the host block. If dwc3 was configured for
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* host-only mode, then we can return early.
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*/
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if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
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return 0;
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reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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reg |= DWC3_DCTL_CSFTRST;
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dwc3_writel(dwc->regs, DWC3_DCTL, reg);
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/*
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* For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
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* is cleared only after all the clocks are synchronized. This can
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* take a little more than 50ms. Set the polling rate at 20ms
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* for 10 times instead.
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*/
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if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
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retries = 10;
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do {
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reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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if (!(reg & DWC3_DCTL_CSFTRST))
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goto done;
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if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
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msleep(20);
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else
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udelay(1);
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} while (--retries);
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phy_exit(dwc->usb3_generic_phy);
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phy_exit(dwc->usb2_generic_phy);
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return -ETIMEDOUT;
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done:
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/*
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* For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
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* is cleared, we must wait at least 50ms before accessing the PHY
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* domain (synchronization delay).
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*/
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if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
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msleep(50);
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return 0;
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}
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/*
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* dwc3_frame_length_adjustment - Adjusts frame length if required
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* @dwc3: Pointer to our controller context structure
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*/
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static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
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{
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u32 reg;
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u32 dft;
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if (DWC3_VER_IS_PRIOR(DWC3, 250A))
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return;
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if (dwc->fladj == 0)
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return;
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reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
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dft = reg & DWC3_GFLADJ_30MHZ_MASK;
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if (dft != dwc->fladj) {
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reg &= ~DWC3_GFLADJ_30MHZ_MASK;
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reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
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dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
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}
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}
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/**
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* dwc3_free_one_event_buffer - Frees one event buffer
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* @dwc: Pointer to our controller context structure
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* @evt: Pointer to event buffer to be freed
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*/
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static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
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struct dwc3_event_buffer *evt)
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{
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dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
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}
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/**
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* dwc3_alloc_one_event_buffer - Allocates one event buffer structure
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* @dwc: Pointer to our controller context structure
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* @length: size of the event buffer
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*
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* Returns a pointer to the allocated event buffer structure on success
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* otherwise ERR_PTR(errno).
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*/
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static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
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unsigned length)
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{
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struct dwc3_event_buffer *evt;
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evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
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if (!evt)
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return ERR_PTR(-ENOMEM);
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evt->dwc = dwc;
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evt->length = length;
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evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
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if (!evt->cache)
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return ERR_PTR(-ENOMEM);
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evt->buf = dma_alloc_coherent(dwc->sysdev, length,
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&evt->dma, GFP_KERNEL);
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if (!evt->buf)
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return ERR_PTR(-ENOMEM);
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return evt;
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}
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/**
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* dwc3_free_event_buffers - frees all allocated event buffers
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* @dwc: Pointer to our controller context structure
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*/
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static void dwc3_free_event_buffers(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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evt = dwc->ev_buf;
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if (evt)
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dwc3_free_one_event_buffer(dwc, evt);
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}
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/**
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* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
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* @dwc: pointer to our controller context structure
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* @length: size of event buffer
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*
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* Returns 0 on success otherwise negative errno. In the error case, dwc
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* may contain some buffers allocated but not all which were requested.
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*/
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static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
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{
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struct dwc3_event_buffer *evt;
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evt = dwc3_alloc_one_event_buffer(dwc, length);
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if (IS_ERR(evt)) {
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dev_err(dwc->dev, "can't allocate event buffer\n");
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return PTR_ERR(evt);
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}
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dwc->ev_buf = evt;
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return 0;
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}
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/**
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* dwc3_event_buffers_setup - setup our allocated event buffers
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* @dwc: pointer to our controller context structure
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*
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* Returns 0 on success otherwise negative errno.
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*/
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int dwc3_event_buffers_setup(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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evt = dwc->ev_buf;
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evt->lpos = 0;
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dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
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lower_32_bits(evt->dma));
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dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
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upper_32_bits(evt->dma));
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dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
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DWC3_GEVNTSIZ_SIZE(evt->length));
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dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
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return 0;
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}
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void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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evt = dwc->ev_buf;
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evt->lpos = 0;
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dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
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dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
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dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
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| DWC3_GEVNTSIZ_SIZE(0));
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dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
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}
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static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
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{
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if (!dwc->has_hibernation)
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return 0;
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if (!dwc->nr_scratch)
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return 0;
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dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
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DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
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if (!dwc->scratchbuf)
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return -ENOMEM;
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return 0;
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}
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static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
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{
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dma_addr_t scratch_addr;
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u32 param;
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int ret;
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if (!dwc->has_hibernation)
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return 0;
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if (!dwc->nr_scratch)
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return 0;
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/* should never fall here */
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if (!WARN_ON(dwc->scratchbuf))
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return 0;
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scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
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dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
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DMA_BIDIRECTIONAL);
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|
if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
|
|
dev_err(dwc->sysdev, "failed to map scratch buffer\n");
|
|
ret = -EFAULT;
|
|
goto err0;
|
|
}
|
|
|
|
dwc->scratch_addr = scratch_addr;
|
|
|
|
param = lower_32_bits(scratch_addr);
|
|
|
|
ret = dwc3_send_gadget_generic_command(dwc,
|
|
DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
|
|
if (ret < 0)
|
|
goto err1;
|
|
|
|
param = upper_32_bits(scratch_addr);
|
|
|
|
ret = dwc3_send_gadget_generic_command(dwc,
|
|
DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
|
|
if (ret < 0)
|
|
goto err1;
|
|
|
|
return 0;
|
|
|
|
err1:
|
|
dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
|
|
DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
|
|
|
|
err0:
|
|
return ret;
|
|
}
|
|
|
|
static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
|
|
{
|
|
if (!dwc->has_hibernation)
|
|
return;
|
|
|
|
if (!dwc->nr_scratch)
|
|
return;
|
|
|
|
/* should never fall here */
|
|
if (!WARN_ON(dwc->scratchbuf))
|
|
return;
|
|
|
|
dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
|
|
DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
|
|
kfree(dwc->scratchbuf);
|
|
}
|
|
|
|
static void dwc3_core_num_eps(struct dwc3 *dwc)
|
|
{
|
|
struct dwc3_hwparams *parms = &dwc->hwparams;
|
|
|
|
dwc->num_eps = DWC3_NUM_EPS(parms);
|
|
}
|
|
|
|
static void dwc3_cache_hwparams(struct dwc3 *dwc)
|
|
{
|
|
struct dwc3_hwparams *parms = &dwc->hwparams;
|
|
|
|
parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
|
|
parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
|
|
parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
|
|
parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
|
|
parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
|
|
parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
|
|
parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
|
|
parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
|
|
parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
|
|
}
|
|
|
|
static int dwc3_core_ulpi_init(struct dwc3 *dwc)
|
|
{
|
|
int intf;
|
|
int ret = 0;
|
|
|
|
intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
|
|
|
|
if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
|
|
(intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
|
|
dwc->hsphy_interface &&
|
|
!strncmp(dwc->hsphy_interface, "ulpi", 4)))
|
|
ret = dwc3_ulpi_init(dwc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
|
|
* @dwc: Pointer to our controller context structure
|
|
*
|
|
* Returns 0 on success. The USB PHY interfaces are configured but not
|
|
* initialized. The PHY interfaces and the PHYs get initialized together with
|
|
* the core in dwc3_core_init.
|
|
*/
|
|
static int dwc3_phy_setup(struct dwc3 *dwc)
|
|
{
|
|
unsigned int hw_mode;
|
|
u32 reg;
|
|
|
|
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
|
|
|
|
/*
|
|
* Make sure UX_EXIT_PX is cleared as that causes issues with some
|
|
* PHYs. Also, this bit is not supposed to be used in normal operation.
|
|
*/
|
|
reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
|
|
|
|
/*
|
|
* Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
|
|
* to '0' during coreConsultant configuration. So default value
|
|
* will be '0' when the core is reset. Application needs to set it
|
|
* to '1' after the core initialization is completed.
|
|
*/
|
|
if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
|
|
reg |= DWC3_GUSB3PIPECTL_SUSPHY;
|
|
|
|
/*
|
|
* For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
|
|
* power-on reset, and it can be set after core initialization, which is
|
|
* after device soft-reset during initialization.
|
|
*/
|
|
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
|
|
reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
|
|
|
|
if (dwc->u2ss_inp3_quirk)
|
|
reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
|
|
|
|
if (dwc->dis_rxdet_inp3_quirk)
|
|
reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
|
|
|
|
if (dwc->req_p1p2p3_quirk)
|
|
reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
|
|
|
|
if (dwc->del_p1p2p3_quirk)
|
|
reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
|
|
|
|
if (dwc->del_phy_power_chg_quirk)
|
|
reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
|
|
|
|
if (dwc->lfps_filter_quirk)
|
|
reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
|
|
|
|
if (dwc->rx_detect_poll_quirk)
|
|
reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
|
|
|
|
if (dwc->tx_de_emphasis_quirk)
|
|
reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
|
|
|
|
if (dwc->dis_u3_susphy_quirk)
|
|
reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
|
|
|
|
if (dwc->dis_del_phy_power_chg_quirk)
|
|
reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
|
|
/* Select the HS PHY interface */
|
|
switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
|
|
case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
|
|
if (dwc->hsphy_interface &&
|
|
!strncmp(dwc->hsphy_interface, "utmi", 4)) {
|
|
reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
|
|
break;
|
|
} else if (dwc->hsphy_interface &&
|
|
!strncmp(dwc->hsphy_interface, "ulpi", 4)) {
|
|
reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
} else {
|
|
/* Relying on default value. */
|
|
if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
|
|
break;
|
|
}
|
|
fallthrough;
|
|
case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
|
|
default:
|
|
break;
|
|
}
|
|
|
|
switch (dwc->hsphy_mode) {
|
|
case USBPHY_INTERFACE_MODE_UTMI:
|
|
reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
|
|
reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
|
|
break;
|
|
case USBPHY_INTERFACE_MODE_UTMIW:
|
|
reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
|
|
reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
|
|
DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
|
|
* '0' during coreConsultant configuration. So default value will
|
|
* be '0' when the core is reset. Application needs to set it to
|
|
* '1' after the core initialization is completed.
|
|
*/
|
|
if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
|
|
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
/*
|
|
* For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
|
|
* power-on reset, and it can be set after core initialization, which is
|
|
* after device soft-reset during initialization.
|
|
*/
|
|
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
|
|
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
if (dwc->dis_u2_susphy_quirk)
|
|
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
if (dwc->dis_enblslpm_quirk)
|
|
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
|
|
else
|
|
reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
|
|
|
|
if (dwc->dis_u2_freeclk_exists_quirk)
|
|
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dwc3_core_exit(struct dwc3 *dwc)
|
|
{
|
|
dwc3_event_buffers_cleanup(dwc);
|
|
|
|
usb_phy_shutdown(dwc->usb2_phy);
|
|
usb_phy_shutdown(dwc->usb3_phy);
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
phy_exit(dwc->usb3_generic_phy);
|
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 1);
|
|
usb_phy_set_suspend(dwc->usb3_phy, 1);
|
|
phy_power_off(dwc->usb2_generic_phy);
|
|
phy_power_off(dwc->usb3_generic_phy);
|
|
clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
|
|
reset_control_assert(dwc->reset);
|
|
}
|
|
|
|
static bool dwc3_core_is_valid(struct dwc3 *dwc)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
|
|
dwc->ip = DWC3_GSNPS_ID(reg);
|
|
|
|
/* This should read as U3 followed by revision number */
|
|
if (DWC3_IP_IS(DWC3)) {
|
|
dwc->revision = reg;
|
|
} else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
|
|
dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
|
|
dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
|
|
} else {
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static void dwc3_core_setup_global_control(struct dwc3 *dwc)
|
|
{
|
|
u32 hwparams4 = dwc->hwparams.hwparams4;
|
|
u32 reg;
|
|
|
|
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
|
|
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
|
|
|
|
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
|
|
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
|
|
/**
|
|
* WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
|
|
* issue which would cause xHCI compliance tests to fail.
|
|
*
|
|
* Because of that we cannot enable clock gating on such
|
|
* configurations.
|
|
*
|
|
* Refers to:
|
|
*
|
|
* STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
|
|
* SOF/ITP Mode Used
|
|
*/
|
|
if ((dwc->dr_mode == USB_DR_MODE_HOST ||
|
|
dwc->dr_mode == USB_DR_MODE_OTG) &&
|
|
DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
|
|
reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
|
|
else
|
|
reg &= ~DWC3_GCTL_DSBLCLKGTNG;
|
|
break;
|
|
case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
|
|
/* enable hibernation here */
|
|
dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
|
|
|
|
/*
|
|
* REVISIT Enabling this bit so that host-mode hibernation
|
|
* will work. Device-mode hibernation is not yet implemented.
|
|
*/
|
|
reg |= DWC3_GCTL_GBLHIBERNATIONEN;
|
|
break;
|
|
default:
|
|
/* nothing */
|
|
break;
|
|
}
|
|
|
|
/* check if current dwc3 is on simulation board */
|
|
if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
|
|
dev_info(dwc->dev, "Running with FPGA optimizations\n");
|
|
dwc->is_fpga = true;
|
|
}
|
|
|
|
WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
|
|
"disable_scramble cannot be used on non-FPGA builds\n");
|
|
|
|
if (dwc->disable_scramble_quirk && dwc->is_fpga)
|
|
reg |= DWC3_GCTL_DISSCRAMBLE;
|
|
else
|
|
reg &= ~DWC3_GCTL_DISSCRAMBLE;
|
|
|
|
if (dwc->u2exit_lfps_quirk)
|
|
reg |= DWC3_GCTL_U2EXIT_LFPS;
|
|
|
|
/*
|
|
* WORKAROUND: DWC3 revisions <1.90a have a bug
|
|
* where the device can fail to connect at SuperSpeed
|
|
* and falls back to high-speed mode which causes
|
|
* the device to enter a Connect/Disconnect loop
|
|
*/
|
|
if (DWC3_VER_IS_PRIOR(DWC3, 190A))
|
|
reg |= DWC3_GCTL_U2RSTECN;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
|
|
}
|
|
|
|
static int dwc3_core_get_phy(struct dwc3 *dwc);
|
|
static int dwc3_core_ulpi_init(struct dwc3 *dwc);
|
|
|
|
/* set global incr burst type configuration registers */
|
|
static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
|
|
{
|
|
struct device *dev = dwc->dev;
|
|
/* incrx_mode : for INCR burst type. */
|
|
bool incrx_mode;
|
|
/* incrx_size : for size of INCRX burst. */
|
|
u32 incrx_size;
|
|
u32 *vals;
|
|
u32 cfg;
|
|
int ntype;
|
|
int ret;
|
|
int i;
|
|
|
|
cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
|
|
|
|
/*
|
|
* Handle property "snps,incr-burst-type-adjustment".
|
|
* Get the number of value from this property:
|
|
* result <= 0, means this property is not supported.
|
|
* result = 1, means INCRx burst mode supported.
|
|
* result > 1, means undefined length burst mode supported.
|
|
*/
|
|
ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
|
|
if (ntype <= 0)
|
|
return;
|
|
|
|
vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
|
|
if (!vals) {
|
|
dev_err(dev, "Error to get memory\n");
|
|
return;
|
|
}
|
|
|
|
/* Get INCR burst type, and parse it */
|
|
ret = device_property_read_u32_array(dev,
|
|
"snps,incr-burst-type-adjustment", vals, ntype);
|
|
if (ret) {
|
|
kfree(vals);
|
|
dev_err(dev, "Error to get property\n");
|
|
return;
|
|
}
|
|
|
|
incrx_size = *vals;
|
|
|
|
if (ntype > 1) {
|
|
/* INCRX (undefined length) burst mode */
|
|
incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
|
|
for (i = 1; i < ntype; i++) {
|
|
if (vals[i] > incrx_size)
|
|
incrx_size = vals[i];
|
|
}
|
|
} else {
|
|
/* INCRX burst mode */
|
|
incrx_mode = INCRX_BURST_MODE;
|
|
}
|
|
|
|
kfree(vals);
|
|
|
|
/* Enable Undefined Length INCR Burst and Enable INCRx Burst */
|
|
cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
|
|
if (incrx_mode)
|
|
cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
|
|
switch (incrx_size) {
|
|
case 256:
|
|
cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
|
|
break;
|
|
case 128:
|
|
cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
|
|
break;
|
|
case 64:
|
|
cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
|
|
break;
|
|
case 32:
|
|
cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
|
|
break;
|
|
case 16:
|
|
cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
|
|
break;
|
|
case 8:
|
|
cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
|
|
break;
|
|
case 4:
|
|
cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
|
|
break;
|
|
case 1:
|
|
break;
|
|
default:
|
|
dev_err(dev, "Invalid property\n");
|
|
break;
|
|
}
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
|
|
}
|
|
|
|
/**
|
|
* dwc3_core_init - Low-level initialization of DWC3 Core
|
|
* @dwc: Pointer to our controller context structure
|
|
*
|
|
* Returns 0 on success otherwise negative errno.
|
|
*/
|
|
static int dwc3_core_init(struct dwc3 *dwc)
|
|
{
|
|
unsigned int hw_mode;
|
|
u32 reg;
|
|
int ret;
|
|
|
|
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
|
|
|
|
/*
|
|
* Write Linux Version Code to our GUID register so it's easy to figure
|
|
* out which kernel version a bug was found.
|
|
*/
|
|
dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
|
|
|
|
ret = dwc3_phy_setup(dwc);
|
|
if (ret)
|
|
goto err0;
|
|
|
|
if (!dwc->ulpi_ready) {
|
|
ret = dwc3_core_ulpi_init(dwc);
|
|
if (ret)
|
|
goto err0;
|
|
dwc->ulpi_ready = true;
|
|
}
|
|
|
|
if (!dwc->phys_ready) {
|
|
ret = dwc3_core_get_phy(dwc);
|
|
if (ret)
|
|
goto err0a;
|
|
dwc->phys_ready = true;
|
|
}
|
|
|
|
ret = dwc3_core_soft_reset(dwc);
|
|
if (ret)
|
|
goto err0a;
|
|
|
|
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
|
|
!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
|
|
if (!dwc->dis_u3_susphy_quirk) {
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
|
|
reg |= DWC3_GUSB3PIPECTL_SUSPHY;
|
|
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
|
|
}
|
|
|
|
if (!dwc->dis_u2_susphy_quirk) {
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
}
|
|
}
|
|
|
|
dwc3_core_setup_global_control(dwc);
|
|
dwc3_core_num_eps(dwc);
|
|
|
|
ret = dwc3_setup_scratch_buffers(dwc);
|
|
if (ret)
|
|
goto err1;
|
|
|
|
/* Adjust Frame Length */
|
|
dwc3_frame_length_adjustment(dwc);
|
|
|
|
dwc3_set_incr_burst_type(dwc);
|
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 0);
|
|
usb_phy_set_suspend(dwc->usb3_phy, 0);
|
|
ret = phy_power_on(dwc->usb2_generic_phy);
|
|
if (ret < 0)
|
|
goto err2;
|
|
|
|
ret = phy_power_on(dwc->usb3_generic_phy);
|
|
if (ret < 0)
|
|
goto err3;
|
|
|
|
ret = dwc3_event_buffers_setup(dwc);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to setup event buffers\n");
|
|
goto err4;
|
|
}
|
|
|
|
/*
|
|
* ENDXFER polling is available on version 3.10a and later of
|
|
* the DWC_usb3 controller. It is NOT available in the
|
|
* DWC_usb31 controller.
|
|
*/
|
|
if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
|
|
reg |= DWC3_GUCTL2_RST_ACTBITLATER;
|
|
dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
|
|
}
|
|
|
|
if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
|
|
|
|
/*
|
|
* Enable hardware control of sending remote wakeup
|
|
* in HS when the device is in the L1 state.
|
|
*/
|
|
if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
|
|
reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
|
|
|
|
if (dwc->dis_tx_ipgap_linecheck_quirk)
|
|
reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
|
|
|
|
if (dwc->parkmode_disable_ss_quirk)
|
|
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
|
|
}
|
|
|
|
if (dwc->dr_mode == USB_DR_MODE_HOST ||
|
|
dwc->dr_mode == USB_DR_MODE_OTG) {
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
|
|
|
|
/*
|
|
* Enable Auto retry Feature to make the controller operating in
|
|
* Host mode on seeing transaction errors(CRC errors or internal
|
|
* overrun scenerios) on IN transfers to reply to the device
|
|
* with a non-terminating retry ACK (i.e, an ACK transcation
|
|
* packet with Retry=1 & Nump != 0)
|
|
*/
|
|
reg |= DWC3_GUCTL_HSTINAUTORETRY;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
|
|
}
|
|
|
|
/*
|
|
* Must config both number of packets and max burst settings to enable
|
|
* RX and/or TX threshold.
|
|
*/
|
|
if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
|
|
u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
|
|
u8 rx_maxburst = dwc->rx_max_burst_prd;
|
|
u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
|
|
u8 tx_maxburst = dwc->tx_max_burst_prd;
|
|
|
|
if (rx_thr_num && rx_maxburst) {
|
|
reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
|
|
reg |= DWC31_RXTHRNUMPKTSEL_PRD;
|
|
|
|
reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
|
|
reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
|
|
|
|
reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
|
|
reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
|
|
}
|
|
|
|
if (tx_thr_num && tx_maxburst) {
|
|
reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
|
|
reg |= DWC31_TXTHRNUMPKTSEL_PRD;
|
|
|
|
reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
|
|
reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
|
|
|
|
reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
|
|
reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
err4:
|
|
phy_power_off(dwc->usb3_generic_phy);
|
|
|
|
err3:
|
|
phy_power_off(dwc->usb2_generic_phy);
|
|
|
|
err2:
|
|
usb_phy_set_suspend(dwc->usb2_phy, 1);
|
|
usb_phy_set_suspend(dwc->usb3_phy, 1);
|
|
|
|
err1:
|
|
usb_phy_shutdown(dwc->usb2_phy);
|
|
usb_phy_shutdown(dwc->usb3_phy);
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
phy_exit(dwc->usb3_generic_phy);
|
|
|
|
err0a:
|
|
dwc3_ulpi_exit(dwc);
|
|
|
|
err0:
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_core_get_phy(struct dwc3 *dwc)
|
|
{
|
|
struct device *dev = dwc->dev;
|
|
struct device_node *node = dev->of_node;
|
|
int ret;
|
|
|
|
if (node) {
|
|
dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
|
|
dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
|
|
} else {
|
|
dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
|
|
dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
|
|
}
|
|
|
|
if (IS_ERR(dwc->usb2_phy)) {
|
|
ret = PTR_ERR(dwc->usb2_phy);
|
|
if (ret == -ENXIO || ret == -ENODEV) {
|
|
dwc->usb2_phy = NULL;
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
return ret;
|
|
} else {
|
|
dev_err(dev, "no usb2 phy configured\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (IS_ERR(dwc->usb3_phy)) {
|
|
ret = PTR_ERR(dwc->usb3_phy);
|
|
if (ret == -ENXIO || ret == -ENODEV) {
|
|
dwc->usb3_phy = NULL;
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
return ret;
|
|
} else {
|
|
dev_err(dev, "no usb3 phy configured\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
|
|
if (IS_ERR(dwc->usb2_generic_phy)) {
|
|
ret = PTR_ERR(dwc->usb2_generic_phy);
|
|
if (ret == -ENOSYS || ret == -ENODEV) {
|
|
dwc->usb2_generic_phy = NULL;
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
return ret;
|
|
} else {
|
|
dev_err(dev, "no usb2 phy configured\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
|
|
if (IS_ERR(dwc->usb3_generic_phy)) {
|
|
ret = PTR_ERR(dwc->usb3_generic_phy);
|
|
if (ret == -ENOSYS || ret == -ENODEV) {
|
|
dwc->usb3_generic_phy = NULL;
|
|
} else if (ret == -EPROBE_DEFER) {
|
|
return ret;
|
|
} else {
|
|
dev_err(dev, "no usb3 phy configured\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_core_init_mode(struct dwc3 *dwc)
|
|
{
|
|
struct device *dev = dwc->dev;
|
|
int ret;
|
|
|
|
switch (dwc->dr_mode) {
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
|
|
|
|
if (dwc->usb2_phy)
|
|
otg_set_vbus(dwc->usb2_phy->otg, false);
|
|
phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
|
|
phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
|
|
|
|
ret = dwc3_gadget_init(dwc);
|
|
if (ret) {
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to initialize gadget\n");
|
|
return ret;
|
|
}
|
|
break;
|
|
case USB_DR_MODE_HOST:
|
|
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
|
|
|
|
if (dwc->usb2_phy)
|
|
otg_set_vbus(dwc->usb2_phy->otg, true);
|
|
phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
|
|
phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
|
|
|
|
ret = dwc3_host_init(dwc);
|
|
if (ret) {
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to initialize host\n");
|
|
return ret;
|
|
}
|
|
break;
|
|
case USB_DR_MODE_OTG:
|
|
INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
|
|
ret = dwc3_drd_init(dwc);
|
|
if (ret) {
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to initialize dual-role\n");
|
|
return ret;
|
|
}
|
|
break;
|
|
default:
|
|
dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dwc3_core_exit_mode(struct dwc3 *dwc)
|
|
{
|
|
switch (dwc->dr_mode) {
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
dwc3_gadget_exit(dwc);
|
|
break;
|
|
case USB_DR_MODE_HOST:
|
|
dwc3_host_exit(dwc);
|
|
break;
|
|
case USB_DR_MODE_OTG:
|
|
dwc3_drd_exit(dwc);
|
|
break;
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
|
|
/* de-assert DRVVBUS for HOST and OTG mode */
|
|
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
|
|
}
|
|
|
|
static void dwc3_get_properties(struct dwc3 *dwc)
|
|
{
|
|
struct device *dev = dwc->dev;
|
|
u8 lpm_nyet_threshold;
|
|
u8 tx_de_emphasis;
|
|
u8 hird_threshold;
|
|
u8 rx_thr_num_pkt_prd;
|
|
u8 rx_max_burst_prd;
|
|
u8 tx_thr_num_pkt_prd;
|
|
u8 tx_max_burst_prd;
|
|
|
|
/* default to highest possible threshold */
|
|
lpm_nyet_threshold = 0xf;
|
|
|
|
/* default to -3.5dB de-emphasis */
|
|
tx_de_emphasis = 1;
|
|
|
|
/*
|
|
* default to assert utmi_sleep_n and use maximum allowed HIRD
|
|
* threshold value of 0b1100
|
|
*/
|
|
hird_threshold = 12;
|
|
|
|
dwc->maximum_speed = usb_get_maximum_speed(dev);
|
|
dwc->dr_mode = usb_get_dr_mode(dev);
|
|
dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
|
|
|
|
dwc->sysdev_is_parent = device_property_read_bool(dev,
|
|
"linux,sysdev_is_parent");
|
|
if (dwc->sysdev_is_parent)
|
|
dwc->sysdev = dwc->dev->parent;
|
|
else
|
|
dwc->sysdev = dwc->dev;
|
|
|
|
dwc->has_lpm_erratum = device_property_read_bool(dev,
|
|
"snps,has-lpm-erratum");
|
|
device_property_read_u8(dev, "snps,lpm-nyet-threshold",
|
|
&lpm_nyet_threshold);
|
|
dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
|
|
"snps,is-utmi-l1-suspend");
|
|
device_property_read_u8(dev, "snps,hird-threshold",
|
|
&hird_threshold);
|
|
dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
|
|
"snps,dis-start-transfer-quirk");
|
|
dwc->usb3_lpm_capable = device_property_read_bool(dev,
|
|
"snps,usb3_lpm_capable");
|
|
dwc->usb2_lpm_disable = device_property_read_bool(dev,
|
|
"snps,usb2-lpm-disable");
|
|
device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
|
|
&rx_thr_num_pkt_prd);
|
|
device_property_read_u8(dev, "snps,rx-max-burst-prd",
|
|
&rx_max_burst_prd);
|
|
device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
|
|
&tx_thr_num_pkt_prd);
|
|
device_property_read_u8(dev, "snps,tx-max-burst-prd",
|
|
&tx_max_burst_prd);
|
|
|
|
dwc->disable_scramble_quirk = device_property_read_bool(dev,
|
|
"snps,disable_scramble_quirk");
|
|
dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
|
|
"snps,u2exit_lfps_quirk");
|
|
dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
|
|
"snps,u2ss_inp3_quirk");
|
|
dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
|
|
"snps,req_p1p2p3_quirk");
|
|
dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
|
|
"snps,del_p1p2p3_quirk");
|
|
dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
|
|
"snps,del_phy_power_chg_quirk");
|
|
dwc->lfps_filter_quirk = device_property_read_bool(dev,
|
|
"snps,lfps_filter_quirk");
|
|
dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
|
|
"snps,rx_detect_poll_quirk");
|
|
dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
|
|
"snps,dis_u3_susphy_quirk");
|
|
dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
|
|
"snps,dis_u2_susphy_quirk");
|
|
dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
|
|
"snps,dis_enblslpm_quirk");
|
|
dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
|
|
"snps,dis-u1-entry-quirk");
|
|
dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
|
|
"snps,dis-u2-entry-quirk");
|
|
dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
|
|
"snps,dis_rxdet_inp3_quirk");
|
|
dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
|
|
"snps,dis-u2-freeclk-exists-quirk");
|
|
dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
|
|
"snps,dis-del-phy-power-chg-quirk");
|
|
dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
|
|
"snps,dis-tx-ipgap-linecheck-quirk");
|
|
dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
|
|
"snps,parkmode-disable-ss-quirk");
|
|
|
|
dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
|
|
"snps,tx_de_emphasis_quirk");
|
|
device_property_read_u8(dev, "snps,tx_de_emphasis",
|
|
&tx_de_emphasis);
|
|
device_property_read_string(dev, "snps,hsphy_interface",
|
|
&dwc->hsphy_interface);
|
|
device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
|
|
&dwc->fladj);
|
|
|
|
dwc->dis_metastability_quirk = device_property_read_bool(dev,
|
|
"snps,dis_metastability_quirk");
|
|
|
|
dwc->dis_split_quirk = device_property_read_bool(dev,
|
|
"snps,dis-split-quirk");
|
|
|
|
dwc->lpm_nyet_threshold = lpm_nyet_threshold;
|
|
dwc->tx_de_emphasis = tx_de_emphasis;
|
|
|
|
dwc->hird_threshold = hird_threshold;
|
|
|
|
dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
|
|
dwc->rx_max_burst_prd = rx_max_burst_prd;
|
|
|
|
dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
|
|
dwc->tx_max_burst_prd = tx_max_burst_prd;
|
|
|
|
dwc->imod_interval = 0;
|
|
}
|
|
|
|
/* check whether the core supports IMOD */
|
|
bool dwc3_has_imod(struct dwc3 *dwc)
|
|
{
|
|
return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
|
|
DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
|
|
DWC3_IP_IS(DWC32);
|
|
}
|
|
|
|
static void dwc3_check_params(struct dwc3 *dwc)
|
|
{
|
|
struct device *dev = dwc->dev;
|
|
unsigned int hwparam_gen =
|
|
DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
|
|
|
|
/* Check for proper value of imod_interval */
|
|
if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
|
|
dev_warn(dwc->dev, "Interrupt moderation not supported\n");
|
|
dwc->imod_interval = 0;
|
|
}
|
|
|
|
/*
|
|
* Workaround for STAR 9000961433 which affects only version
|
|
* 3.00a of the DWC_usb3 core. This prevents the controller
|
|
* interrupt from being masked while handling events. IMOD
|
|
* allows us to work around this issue. Enable it for the
|
|
* affected version.
|
|
*/
|
|
if (!dwc->imod_interval &&
|
|
DWC3_VER_IS(DWC3, 300A))
|
|
dwc->imod_interval = 1;
|
|
|
|
/* Check the maximum_speed parameter */
|
|
switch (dwc->maximum_speed) {
|
|
case USB_SPEED_LOW:
|
|
case USB_SPEED_FULL:
|
|
case USB_SPEED_HIGH:
|
|
break;
|
|
case USB_SPEED_SUPER:
|
|
if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
|
|
dev_warn(dev, "UDC doesn't support Gen 1\n");
|
|
break;
|
|
case USB_SPEED_SUPER_PLUS:
|
|
if ((DWC3_IP_IS(DWC32) &&
|
|
hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
|
|
(!DWC3_IP_IS(DWC32) &&
|
|
hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
|
|
dev_warn(dev, "UDC doesn't support SSP\n");
|
|
break;
|
|
default:
|
|
dev_err(dev, "invalid maximum_speed parameter %d\n",
|
|
dwc->maximum_speed);
|
|
fallthrough;
|
|
case USB_SPEED_UNKNOWN:
|
|
switch (hwparam_gen) {
|
|
case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
|
|
dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
|
|
break;
|
|
case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
|
|
if (DWC3_IP_IS(DWC32))
|
|
dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
|
|
else
|
|
dwc->maximum_speed = USB_SPEED_SUPER;
|
|
break;
|
|
case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
|
|
dwc->maximum_speed = USB_SPEED_HIGH;
|
|
break;
|
|
default:
|
|
dwc->maximum_speed = USB_SPEED_SUPER;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int dwc3_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct resource *res, dwc_res;
|
|
struct dwc3 *dwc;
|
|
|
|
int ret;
|
|
|
|
void __iomem *regs;
|
|
|
|
dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
|
|
if (!dwc)
|
|
return -ENOMEM;
|
|
|
|
dwc->dev = dev;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(dev, "missing memory resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
dwc->xhci_resources[0].start = res->start;
|
|
dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
|
|
DWC3_XHCI_REGS_END;
|
|
dwc->xhci_resources[0].flags = res->flags;
|
|
dwc->xhci_resources[0].name = res->name;
|
|
|
|
/*
|
|
* Request memory region but exclude xHCI regs,
|
|
* since it will be requested by the xhci-plat driver.
|
|
*/
|
|
dwc_res = *res;
|
|
dwc_res.start += DWC3_GLOBALS_REGS_START;
|
|
|
|
regs = devm_ioremap_resource(dev, &dwc_res);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
|
|
dwc->regs = regs;
|
|
dwc->regs_size = resource_size(&dwc_res);
|
|
|
|
dwc3_get_properties(dwc);
|
|
|
|
dwc->reset = devm_reset_control_array_get(dev, true, true);
|
|
if (IS_ERR(dwc->reset))
|
|
return PTR_ERR(dwc->reset);
|
|
|
|
if (dev->of_node) {
|
|
ret = devm_clk_bulk_get_all(dev, &dwc->clks);
|
|
if (ret == -EPROBE_DEFER)
|
|
return ret;
|
|
/*
|
|
* Clocks are optional, but new DT platforms should support all
|
|
* clocks as required by the DT-binding.
|
|
*/
|
|
if (ret < 0)
|
|
dwc->num_clks = 0;
|
|
else
|
|
dwc->num_clks = ret;
|
|
|
|
}
|
|
|
|
ret = reset_control_deassert(dwc->reset);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
|
|
if (ret)
|
|
goto assert_reset;
|
|
|
|
if (!dwc3_core_is_valid(dwc)) {
|
|
dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
|
|
ret = -ENODEV;
|
|
goto disable_clks;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, dwc);
|
|
dwc3_cache_hwparams(dwc);
|
|
|
|
spin_lock_init(&dwc->lock);
|
|
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_use_autosuspend(dev);
|
|
pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
|
|
pm_runtime_enable(dev);
|
|
ret = pm_runtime_get_sync(dev);
|
|
if (ret < 0)
|
|
goto err1;
|
|
|
|
pm_runtime_forbid(dev);
|
|
|
|
ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
|
|
if (ret) {
|
|
dev_err(dwc->dev, "failed to allocate event buffers\n");
|
|
ret = -ENOMEM;
|
|
goto err2;
|
|
}
|
|
|
|
ret = dwc3_get_dr_mode(dwc);
|
|
if (ret)
|
|
goto err3;
|
|
|
|
ret = dwc3_alloc_scratch_buffers(dwc);
|
|
if (ret)
|
|
goto err3;
|
|
|
|
ret = dwc3_core_init(dwc);
|
|
if (ret) {
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "failed to initialize core: %d\n", ret);
|
|
goto err4;
|
|
}
|
|
|
|
dwc3_check_params(dwc);
|
|
|
|
ret = dwc3_core_init_mode(dwc);
|
|
if (ret)
|
|
goto err5;
|
|
|
|
dwc3_debugfs_init(dwc);
|
|
pm_runtime_put(dev);
|
|
|
|
return 0;
|
|
|
|
err5:
|
|
dwc3_event_buffers_cleanup(dwc);
|
|
|
|
usb_phy_shutdown(dwc->usb2_phy);
|
|
usb_phy_shutdown(dwc->usb3_phy);
|
|
phy_exit(dwc->usb2_generic_phy);
|
|
phy_exit(dwc->usb3_generic_phy);
|
|
|
|
usb_phy_set_suspend(dwc->usb2_phy, 1);
|
|
usb_phy_set_suspend(dwc->usb3_phy, 1);
|
|
phy_power_off(dwc->usb2_generic_phy);
|
|
phy_power_off(dwc->usb3_generic_phy);
|
|
|
|
dwc3_ulpi_exit(dwc);
|
|
|
|
err4:
|
|
dwc3_free_scratch_buffers(dwc);
|
|
|
|
err3:
|
|
dwc3_free_event_buffers(dwc);
|
|
|
|
err2:
|
|
pm_runtime_allow(&pdev->dev);
|
|
|
|
err1:
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
disable_clks:
|
|
clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
|
|
assert_reset:
|
|
reset_control_assert(dwc->reset);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_remove(struct platform_device *pdev)
|
|
{
|
|
struct dwc3 *dwc = platform_get_drvdata(pdev);
|
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
dwc3_debugfs_exit(dwc);
|
|
dwc3_core_exit_mode(dwc);
|
|
|
|
dwc3_core_exit(dwc);
|
|
dwc3_ulpi_exit(dwc);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
|
|
dwc3_free_event_buffers(dwc);
|
|
dwc3_free_scratch_buffers(dwc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int dwc3_core_init_for_resume(struct dwc3 *dwc)
|
|
{
|
|
int ret;
|
|
|
|
ret = reset_control_deassert(dwc->reset);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
|
|
if (ret)
|
|
goto assert_reset;
|
|
|
|
ret = dwc3_core_init(dwc);
|
|
if (ret)
|
|
goto disable_clks;
|
|
|
|
return 0;
|
|
|
|
disable_clks:
|
|
clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
|
|
assert_reset:
|
|
reset_control_assert(dwc->reset);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
|
|
{
|
|
unsigned long flags;
|
|
u32 reg;
|
|
|
|
switch (dwc->current_dr_role) {
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
|
if (pm_runtime_suspended(dwc->dev))
|
|
break;
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
dwc3_gadget_suspend(dwc);
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
synchronize_irq(dwc->irq_gadget);
|
|
dwc3_core_exit(dwc);
|
|
break;
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
|
if (!PMSG_IS_AUTO(msg)) {
|
|
dwc3_core_exit(dwc);
|
|
break;
|
|
}
|
|
|
|
/* Let controller to suspend HSPHY before PHY driver suspends */
|
|
if (dwc->dis_u2_susphy_quirk ||
|
|
dwc->dis_enblslpm_quirk) {
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
|
|
DWC3_GUSB2PHYCFG_SUSPHY;
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
|
|
/* Give some time for USB2 PHY to suspend */
|
|
usleep_range(5000, 6000);
|
|
}
|
|
|
|
phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
|
|
phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
|
|
break;
|
|
case DWC3_GCTL_PRTCAP_OTG:
|
|
/* do nothing during runtime_suspend */
|
|
if (PMSG_IS_AUTO(msg))
|
|
break;
|
|
|
|
if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
dwc3_gadget_suspend(dwc);
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
synchronize_irq(dwc->irq_gadget);
|
|
}
|
|
|
|
dwc3_otg_exit(dwc);
|
|
dwc3_core_exit(dwc);
|
|
break;
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
|
|
{
|
|
unsigned long flags;
|
|
int ret;
|
|
u32 reg;
|
|
|
|
switch (dwc->current_dr_role) {
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
|
ret = dwc3_core_init_for_resume(dwc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
dwc3_gadget_resume(dwc);
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
break;
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
|
if (!PMSG_IS_AUTO(msg)) {
|
|
ret = dwc3_core_init_for_resume(dwc);
|
|
if (ret)
|
|
return ret;
|
|
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
|
|
break;
|
|
}
|
|
/* Restore GUSB2PHYCFG bits that were modified in suspend */
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
|
|
if (dwc->dis_u2_susphy_quirk)
|
|
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
|
|
|
|
if (dwc->dis_enblslpm_quirk)
|
|
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
|
|
|
|
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
|
|
|
|
phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
|
|
phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
|
|
break;
|
|
case DWC3_GCTL_PRTCAP_OTG:
|
|
/* nothing to do on runtime_resume */
|
|
if (PMSG_IS_AUTO(msg))
|
|
break;
|
|
|
|
ret = dwc3_core_init(dwc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dwc3_set_prtcap(dwc, dwc->current_dr_role);
|
|
|
|
dwc3_otg_init(dwc);
|
|
if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
|
|
dwc3_otg_host_init(dwc);
|
|
} else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
|
|
spin_lock_irqsave(&dwc->lock, flags);
|
|
dwc3_gadget_resume(dwc);
|
|
spin_unlock_irqrestore(&dwc->lock, flags);
|
|
}
|
|
|
|
break;
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_runtime_checks(struct dwc3 *dwc)
|
|
{
|
|
switch (dwc->current_dr_role) {
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
|
if (dwc->connected)
|
|
return -EBUSY;
|
|
break;
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_runtime_suspend(struct device *dev)
|
|
{
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
if (dwc3_runtime_checks(dwc))
|
|
return -EBUSY;
|
|
|
|
ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
|
|
if (ret)
|
|
return ret;
|
|
|
|
device_init_wakeup(dev, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_runtime_resume(struct device *dev)
|
|
{
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
device_init_wakeup(dev, false);
|
|
|
|
ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
|
|
if (ret)
|
|
return ret;
|
|
|
|
switch (dwc->current_dr_role) {
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
|
dwc3_gadget_process_pending_events(dwc);
|
|
break;
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_runtime_idle(struct device *dev)
|
|
{
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
|
|
switch (dwc->current_dr_role) {
|
|
case DWC3_GCTL_PRTCAP_DEVICE:
|
|
if (dwc3_runtime_checks(dwc))
|
|
return -EBUSY;
|
|
break;
|
|
case DWC3_GCTL_PRTCAP_HOST:
|
|
default:
|
|
/* do nothing */
|
|
break;
|
|
}
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_autosuspend(dev);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM */
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int dwc3_suspend(struct device *dev)
|
|
{
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwc3_resume(struct device *dev)
|
|
{
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
ret = dwc3_resume_common(dwc, PMSG_RESUME);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void dwc3_complete(struct device *dev)
|
|
{
|
|
struct dwc3 *dwc = dev_get_drvdata(dev);
|
|
u32 reg;
|
|
|
|
if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
|
|
dwc->dis_split_quirk) {
|
|
reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
|
|
reg |= DWC3_GUCTL3_SPLITDISABLE;
|
|
dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
|
|
}
|
|
}
|
|
#else
|
|
#define dwc3_complete NULL
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static const struct dev_pm_ops dwc3_dev_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
|
|
.complete = dwc3_complete,
|
|
SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
|
|
dwc3_runtime_idle)
|
|
};
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id of_dwc3_match[] = {
|
|
{
|
|
.compatible = "snps,dwc3"
|
|
},
|
|
{
|
|
.compatible = "synopsys,dwc3"
|
|
},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, of_dwc3_match);
|
|
#endif
|
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
#define ACPI_ID_INTEL_BSW "808622B7"
|
|
|
|
static const struct acpi_device_id dwc3_acpi_match[] = {
|
|
{ ACPI_ID_INTEL_BSW, 0 },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
|
|
#endif
|
|
|
|
static struct platform_driver dwc3_driver = {
|
|
.probe = dwc3_probe,
|
|
.remove = dwc3_remove,
|
|
.driver = {
|
|
.name = "dwc3",
|
|
.of_match_table = of_match_ptr(of_dwc3_match),
|
|
.acpi_match_table = ACPI_PTR(dwc3_acpi_match),
|
|
.pm = &dwc3_dev_pm_ops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(dwc3_driver);
|
|
|
|
MODULE_ALIAS("platform:dwc3");
|
|
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
|