2017-09-12 19:58:20 +00:00
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef _CORE_TYPES_H_
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#define _CORE_TYPES_H_
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#include "dc.h"
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2017-03-21 22:17:12 +00:00
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#include "dce_calcs.h"
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2017-06-15 20:27:42 +00:00
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#include "dcn_calcs.h"
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2017-09-12 19:58:20 +00:00
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#include "ddc_service_types.h"
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#include "dc_bios_types.h"
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2017-06-15 20:27:42 +00:00
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#include "mem_input.h"
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2017-10-02 18:39:42 +00:00
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#include "hubp.h"
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2019-11-06 19:48:35 +00:00
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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2017-06-15 20:27:42 +00:00
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#include "mpc.h"
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2017-08-03 14:20:52 +00:00
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#endif
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2019-02-22 20:54:43 +00:00
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#include "dwb.h"
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#include "mcif_wb.h"
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2020-04-08 17:31:50 +00:00
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#include "panel_cntl.h"
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2017-09-12 19:58:20 +00:00
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#define MAX_CLOCK_SOURCES 7
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2017-07-27 13:55:38 +00:00
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void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
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2017-09-12 19:58:20 +00:00
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uint32_t controller_id);
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#include "grph_object_id.h"
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#include "link_encoder.h"
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#include "stream_encoder.h"
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#include "clock_source.h"
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#include "audio.h"
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2017-08-13 17:50:52 +00:00
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#include "dm_pp_smu.h"
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2019-08-06 21:43:53 +00:00
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#ifdef CONFIG_DRM_AMD_DC_HDCP
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#include "dm_cp_psp.h"
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#endif
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2017-09-12 19:58:20 +00:00
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/************ link *****************/
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struct link_init_data {
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2017-08-01 19:00:25 +00:00
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const struct dc *dc;
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2017-09-12 19:58:20 +00:00
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struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
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uint32_t connector_index; /* this will be mapped to the HPD pins */
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uint32_t link_index; /* this is mapped to DAL display_index
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TODO: remove it when DC is complete. */
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2021-01-26 20:15:33 +00:00
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bool is_dpia_link;
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2017-09-12 19:58:20 +00:00
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};
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2017-07-23 00:05:20 +00:00
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struct dc_link *link_create(const struct link_init_data *init_params);
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void link_destroy(struct dc_link **link);
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2017-09-12 19:58:20 +00:00
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enum dc_status dc_link_validate_mode_timing(
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2017-07-27 13:33:33 +00:00
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const struct dc_stream_state *stream,
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2017-07-23 00:05:20 +00:00
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struct dc_link *link,
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2017-09-12 19:58:20 +00:00
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const struct dc_crtc_timing *timing);
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2017-07-23 00:05:20 +00:00
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void core_link_resume(struct dc_link *link);
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2017-09-12 19:58:20 +00:00
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2017-08-28 18:25:01 +00:00
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void core_link_enable_stream(
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struct dc_state *state,
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struct pipe_ctx *pipe_ctx);
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2017-09-12 19:58:20 +00:00
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2019-07-25 18:43:55 +00:00
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void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
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2017-09-12 19:58:20 +00:00
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2017-07-17 20:04:02 +00:00
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void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
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2017-09-12 19:58:20 +00:00
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/********** DAL Core*********************/
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#include "transform.h"
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2017-10-05 20:47:49 +00:00
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#include "dpp.h"
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2017-09-12 19:58:20 +00:00
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struct resource_pool;
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2017-08-25 20:16:10 +00:00
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struct dc_state;
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2017-09-12 19:58:20 +00:00
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struct resource_context;
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2019-07-26 21:16:47 +00:00
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struct clk_bw_params;
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2017-09-12 19:58:20 +00:00
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struct resource_funcs {
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void (*destroy)(struct resource_pool **pool);
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2018-08-07 18:43:20 +00:00
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void (*link_init)(struct dc_link *link);
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2020-04-08 17:31:50 +00:00
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struct panel_cntl*(*panel_cntl_create)(
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const struct panel_cntl_init_data *panel_cntl_init_data);
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2017-09-12 19:58:20 +00:00
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struct link_encoder *(*link_enc_create)(
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const struct encoder_init_data *init);
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2021-01-05 15:17:05 +00:00
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/* Create a minimal link encoder object with no dc_link object
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* associated with it. */
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struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id);
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2017-02-24 19:19:40 +00:00
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bool (*validate_bandwidth)(
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2017-08-01 19:00:25 +00:00
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struct dc *dc,
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2019-04-01 19:18:29 +00:00
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struct dc_state *context,
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bool fast_validate);
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2020-09-25 14:54:51 +00:00
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void (*calculate_wm_and_dlg)(
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2020-05-27 14:34:38 +00:00
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struct dc *dc, struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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int pipe_cnt,
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int vlevel);
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2021-02-17 16:32:10 +00:00
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void (*update_soc_for_wm_a)(
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struct dc *dc, struct dc_state *context);
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2019-04-17 18:48:25 +00:00
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int (*populate_dml_pipes)(
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struct dc *dc,
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2019-10-24 19:45:44 +00:00
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struct dc_state *context,
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2020-10-23 15:55:32 +00:00
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display_e2e_pipe_params_st *pipes,
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bool fast_validate);
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2019-04-17 18:48:25 +00:00
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2021-01-05 19:25:23 +00:00
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/*
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* Algorithm for assigning available link encoders to links.
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*
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* Update link_enc_assignments table and link_enc_avail list accordingly in
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* struct resource_context.
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*/
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void (*link_encs_assign)(
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struct dc *dc,
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struct dc_state *state,
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struct dc_stream_state *streams[],
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uint8_t stream_count);
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/*
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* Unassign a link encoder from a stream.
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*
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* Update link_enc_assignments table and link_enc_avail list accordingly in
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* struct resource_context.
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*/
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void (*link_enc_unassign)(
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struct dc_state *state,
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struct dc_stream_state *stream);
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2017-07-31 15:29:25 +00:00
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enum dc_status (*validate_global)(
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struct dc *dc,
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2017-08-25 20:16:10 +00:00
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struct dc_state *context);
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2017-07-31 15:29:25 +00:00
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2017-09-12 19:58:20 +00:00
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struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
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2017-08-25 20:16:10 +00:00
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struct dc_state *context,
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2017-04-22 18:17:51 +00:00
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const struct resource_pool *pool,
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2017-07-27 13:33:33 +00:00
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struct dc_stream_state *stream);
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2017-07-31 15:29:25 +00:00
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2017-10-03 16:54:18 +00:00
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enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);
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2017-07-31 15:29:25 +00:00
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enum dc_status (*add_stream_to_ctx)(
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struct dc *dc,
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2017-08-25 20:16:10 +00:00
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struct dc_state *new_ctx,
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2017-07-31 15:29:25 +00:00
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struct dc_stream_state *dc_stream);
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2017-12-14 22:57:56 +00:00
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enum dc_status (*remove_stream_from_ctx)(
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struct dc *dc,
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struct dc_state *new_ctx,
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struct dc_stream_state *stream);
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2020-02-14 22:53:47 +00:00
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enum dc_status (*patch_unknown_plane_state)(
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2018-09-13 19:26:08 +00:00
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struct dc_plane_state *plane_state);
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2019-04-24 19:25:41 +00:00
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struct stream_encoder *(*find_first_free_match_stream_enc_for_link)(
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struct resource_context *res_ctx,
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const struct resource_pool *pool,
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struct dc_stream_state *stream);
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2019-02-22 20:54:43 +00:00
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void (*populate_dml_writeback_from_context)(
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struct dc *dc,
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struct resource_context *res_ctx,
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display_e2e_pipe_params_st *pipes);
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2019-04-24 19:25:41 +00:00
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2019-02-22 20:54:43 +00:00
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void (*set_mcif_arb_params)(
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struct dc *dc,
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struct dc_state *context,
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display_e2e_pipe_params_st *pipes,
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int pipe_cnt);
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2019-07-26 21:09:35 +00:00
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void (*update_bw_bounding_box)(
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struct dc *dc,
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struct clk_bw_params *bw_params);
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2020-11-02 20:37:34 +00:00
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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2020-05-21 16:51:51 +00:00
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bool (*acquire_post_bldn_3dlut)(
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struct resource_context *res_ctx,
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const struct resource_pool *pool,
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int mpcc_id,
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struct dc_3dlut **lut,
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struct dc_transfer_func **shaper);
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bool (*release_post_bldn_3dlut)(
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struct resource_context *res_ctx,
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const struct resource_pool *pool,
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struct dc_3dlut **lut,
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struct dc_transfer_func **shaper);
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#endif
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2020-07-06 18:53:57 +00:00
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enum dc_status (*add_dsc_to_stream_resource)(
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struct dc *dc, struct dc_state *state,
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struct dc_stream_state *stream);
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2017-09-12 19:58:20 +00:00
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};
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struct audio_support{
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bool dp_audio;
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bool hdmi_audio_on_dongle;
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bool hdmi_audio_native;
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};
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2017-01-23 16:49:24 +00:00
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#define NO_UNDERLAY_PIPE -1
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2017-09-12 19:58:20 +00:00
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struct resource_pool {
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struct mem_input *mis[MAX_PIPES];
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2017-10-02 18:39:42 +00:00
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struct hubp *hubps[MAX_PIPES];
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2017-09-12 19:58:20 +00:00
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struct input_pixel_processor *ipps[MAX_PIPES];
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struct transform *transforms[MAX_PIPES];
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2017-10-05 20:47:49 +00:00
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struct dpp *dpps[MAX_PIPES];
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2017-09-12 19:58:20 +00:00
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struct output_pixel_processor *opps[MAX_PIPES];
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struct timing_generator *timing_generators[MAX_PIPES];
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struct stream_encoder *stream_enc[MAX_PIPES * 2];
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2017-10-23 20:01:36 +00:00
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struct hubbub *hubbub;
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2017-07-21 21:46:50 +00:00
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struct mpc *mpc;
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2019-01-15 15:46:46 +00:00
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struct pp_smu_funcs *pp_smu;
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2018-11-30 15:32:01 +00:00
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struct dce_aux *engines[MAX_PIPES];
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2018-07-23 18:12:10 +00:00
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struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
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struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
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bool i2c_hw_buffer_in_use;
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2017-09-12 19:58:20 +00:00
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2019-02-22 20:54:43 +00:00
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struct dwbc *dwbc[MAX_DWB_PIPES];
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struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
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struct {
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unsigned int gsl_0:1;
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unsigned int gsl_1:1;
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unsigned int gsl_2:1;
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} gsl_groups;
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2019-02-25 18:26:34 +00:00
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struct display_stream_compressor *dscs[MAX_PIPES];
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2019-02-22 20:54:43 +00:00
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2017-09-12 19:58:20 +00:00
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unsigned int pipe_count;
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unsigned int underlay_pipe_index;
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unsigned int stream_enc_count;
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2019-02-13 22:56:38 +00:00
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2021-01-05 15:17:05 +00:00
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/* An array for accessing the link encoder objects that have been created.
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* Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA
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*/
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struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS];
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/* Number of DIG link encoder objects created - i.e. number of valid
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* entries in link_encoders array.
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*/
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unsigned int dig_link_enc_count;
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2021-01-05 15:17:05 +00:00
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/* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/
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unsigned int usb4_dpia_count;
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2021-01-05 15:17:05 +00:00
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2021-06-09 19:21:35 +00:00
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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unsigned int hpo_dp_stream_enc_count;
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struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS];
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2021-08-03 17:48:54 +00:00
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unsigned int hpo_dp_link_enc_count;
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struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS];
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2021-06-09 19:21:35 +00:00
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#endif
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2020-11-02 20:37:34 +00:00
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#if defined(CONFIG_DRM_AMD_DC_DCN)
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2020-05-21 16:51:51 +00:00
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struct dc_3dlut *mpc_lut[MAX_PIPES];
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struct dc_transfer_func *mpc_shaper[MAX_PIPES];
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#endif
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2019-02-22 21:50:00 +00:00
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struct {
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unsigned int xtalin_clock_inKhz;
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unsigned int dccg_ref_clock_inKhz;
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unsigned int dchub_ref_clock_inKhz;
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} ref_clocks;
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2018-01-05 18:53:06 +00:00
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unsigned int timing_generator_count;
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2019-02-22 20:54:43 +00:00
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unsigned int mpcc_count;
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2017-09-12 19:58:20 +00:00
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2019-02-22 20:54:43 +00:00
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unsigned int writeback_pipe_count;
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2017-09-12 19:58:20 +00:00
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/*
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* reserved clock source for DP
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*/
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struct clock_source *dp_clock_source;
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struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
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unsigned int clk_src_count;
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2019-06-28 15:40:38 +00:00
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struct audio *audios[MAX_AUDIOS];
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2017-09-12 19:58:20 +00:00
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|
unsigned int audio_count;
|
|
|
|
struct audio_support audio_support;
|
|
|
|
|
2018-09-28 12:42:52 +00:00
|
|
|
struct dccg *dccg;
|
2017-09-12 19:58:20 +00:00
|
|
|
struct irq_service *irqs;
|
|
|
|
|
2017-01-23 21:55:20 +00:00
|
|
|
struct abm *abm;
|
|
|
|
struct dmcu *dmcu;
|
2019-12-12 02:42:03 +00:00
|
|
|
struct dmub_psr *psr;
|
2017-01-23 21:55:20 +00:00
|
|
|
|
2020-11-02 20:37:34 +00:00
|
|
|
#if defined(CONFIG_DRM_AMD_DC_DCN)
|
2020-05-21 16:45:45 +00:00
|
|
|
struct abm *multiple_abms[MAX_PIPES];
|
|
|
|
#endif
|
|
|
|
|
2017-09-12 19:58:20 +00:00
|
|
|
const struct resource_funcs *funcs;
|
|
|
|
const struct resource_caps *res_cap;
|
2019-08-02 21:22:57 +00:00
|
|
|
|
|
|
|
struct ddc_service *oem_device;
|
2017-09-12 19:58:20 +00:00
|
|
|
};
|
|
|
|
|
2018-02-12 20:19:20 +00:00
|
|
|
struct dcn_fe_bandwidth {
|
2018-09-18 18:24:05 +00:00
|
|
|
int dppclk_khz;
|
2019-08-26 19:02:47 +00:00
|
|
|
|
2018-02-12 20:19:20 +00:00
|
|
|
};
|
|
|
|
|
2017-07-30 15:43:06 +00:00
|
|
|
struct stream_resource {
|
2017-07-30 17:55:28 +00:00
|
|
|
struct output_pixel_processor *opp;
|
2019-02-25 18:26:34 +00:00
|
|
|
struct display_stream_compressor *dsc;
|
2017-07-30 17:59:26 +00:00
|
|
|
struct timing_generator *tg;
|
2017-07-30 18:36:12 +00:00
|
|
|
struct stream_encoder *stream_enc;
|
2021-06-09 19:21:35 +00:00
|
|
|
#if defined(CONFIG_DRM_AMD_DC_DCN)
|
|
|
|
struct hpo_dp_stream_encoder *hpo_dp_stream_enc;
|
|
|
|
#endif
|
2017-07-30 18:59:17 +00:00
|
|
|
struct audio *audio;
|
2017-07-30 19:17:43 +00:00
|
|
|
|
|
|
|
struct pixel_clk_params pix_clk_params;
|
2017-07-30 19:58:26 +00:00
|
|
|
struct encoder_info_frame encoder_info_frame;
|
2018-02-23 18:04:13 +00:00
|
|
|
|
|
|
|
struct abm *abm;
|
2019-02-22 20:54:43 +00:00
|
|
|
/* There are only (num_pipes+1)/2 groups. 0 means unassigned,
|
|
|
|
* otherwise it's using group number 'gsl_group-1'
|
|
|
|
*/
|
|
|
|
uint8_t gsl_group;
|
2017-07-30 15:43:06 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct plane_resource {
|
2017-07-30 15:51:21 +00:00
|
|
|
struct scaler_data scl_data;
|
2017-10-02 18:39:42 +00:00
|
|
|
struct hubp *hubp;
|
2017-07-30 15:55:55 +00:00
|
|
|
struct mem_input *mi;
|
|
|
|
struct input_pixel_processor *ipp;
|
|
|
|
struct transform *xfm;
|
2017-10-05 20:47:49 +00:00
|
|
|
struct dpp *dpp;
|
2017-12-19 21:47:02 +00:00
|
|
|
uint8_t mpcc_inst;
|
2018-02-12 20:19:20 +00:00
|
|
|
|
|
|
|
struct dcn_fe_bandwidth bw;
|
2017-07-30 15:43:06 +00:00
|
|
|
};
|
|
|
|
|
2021-11-25 17:30:50 +00:00
|
|
|
/* all mappable hardware resources used to enable a link */
|
|
|
|
struct link_resource {
|
|
|
|
void *dummy;
|
|
|
|
};
|
|
|
|
|
2019-04-08 18:56:29 +00:00
|
|
|
union pipe_update_flags {
|
|
|
|
struct {
|
|
|
|
uint32_t enable : 1;
|
|
|
|
uint32_t disable : 1;
|
|
|
|
uint32_t odm : 1;
|
|
|
|
uint32_t global_sync : 1;
|
|
|
|
uint32_t opp_changed : 1;
|
|
|
|
uint32_t tg_changed : 1;
|
|
|
|
uint32_t mpcc : 1;
|
|
|
|
uint32_t dppclk : 1;
|
|
|
|
uint32_t hubp_interdependent : 1;
|
|
|
|
uint32_t hubp_rq_dlg_ttu : 1;
|
|
|
|
uint32_t gamut_remap : 1;
|
|
|
|
uint32_t scaler : 1;
|
|
|
|
uint32_t viewport : 1;
|
2020-08-13 08:59:24 +00:00
|
|
|
uint32_t plane_changed : 1;
|
2021-05-19 15:28:27 +00:00
|
|
|
uint32_t det_size : 1;
|
2019-04-08 18:56:29 +00:00
|
|
|
} bits;
|
|
|
|
uint32_t raw;
|
|
|
|
};
|
|
|
|
|
2017-09-12 19:58:20 +00:00
|
|
|
struct pipe_ctx {
|
2017-07-27 13:55:38 +00:00
|
|
|
struct dc_plane_state *plane_state;
|
2017-07-27 13:33:33 +00:00
|
|
|
struct dc_stream_state *stream;
|
2017-09-12 19:58:20 +00:00
|
|
|
|
2017-07-30 15:43:06 +00:00
|
|
|
struct plane_resource plane_res;
|
|
|
|
struct stream_resource stream_res;
|
2021-11-25 17:30:50 +00:00
|
|
|
struct link_resource link_res;
|
2017-07-30 15:43:06 +00:00
|
|
|
|
2017-09-12 19:58:20 +00:00
|
|
|
struct clock_source *clock_source;
|
|
|
|
|
|
|
|
struct pll_settings pll_settings;
|
|
|
|
|
|
|
|
uint8_t pipe_idx;
|
2021-11-15 06:51:37 +00:00
|
|
|
uint8_t pipe_idx_syncd;
|
2017-09-12 19:58:20 +00:00
|
|
|
|
|
|
|
struct pipe_ctx *top_pipe;
|
|
|
|
struct pipe_ctx *bottom_pipe;
|
2019-08-06 21:17:28 +00:00
|
|
|
struct pipe_ctx *next_odm_pipe;
|
|
|
|
struct pipe_ctx *prev_odm_pipe;
|
2017-06-01 22:35:54 +00:00
|
|
|
|
2019-11-06 19:48:35 +00:00
|
|
|
#ifdef CONFIG_DRM_AMD_DC_DCN
|
2017-06-15 20:27:42 +00:00
|
|
|
struct _vcs_dpi_display_dlg_regs_st dlg_regs;
|
|
|
|
struct _vcs_dpi_display_ttu_regs_st ttu_regs;
|
|
|
|
struct _vcs_dpi_display_rq_regs_st rq_regs;
|
|
|
|
struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
|
2021-09-08 00:22:13 +00:00
|
|
|
struct _vcs_dpi_display_rq_params_st dml_rq_param;
|
|
|
|
struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param;
|
|
|
|
struct _vcs_dpi_display_e2e_pipe_params_st dml_input;
|
2021-05-19 15:28:27 +00:00
|
|
|
int det_buffer_size_kb;
|
|
|
|
bool unbounded_req;
|
2017-06-15 20:27:42 +00:00
|
|
|
#endif
|
2019-04-08 18:56:29 +00:00
|
|
|
union pipe_update_flags update_flags;
|
2019-02-22 20:54:43 +00:00
|
|
|
struct dwbc *dwbc;
|
|
|
|
struct mcif_wb *mcif_wb;
|
2020-12-16 18:52:19 +00:00
|
|
|
bool vtp_locked;
|
2017-09-12 19:58:20 +00:00
|
|
|
};
|
|
|
|
|
2021-09-02 14:01:02 +00:00
|
|
|
/* Data used for dynamic link encoder assignment.
|
|
|
|
* Tracks current and future assignments; available link encoders;
|
|
|
|
* and mode of operation (whether to use current or future assignments).
|
|
|
|
*/
|
|
|
|
struct link_enc_cfg_context {
|
|
|
|
enum link_enc_cfg_mode mode;
|
|
|
|
struct link_enc_assignment link_enc_assignments[MAX_PIPES];
|
|
|
|
enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS];
|
|
|
|
struct link_enc_assignment transient_assignments[MAX_PIPES];
|
|
|
|
};
|
|
|
|
|
2017-09-12 19:58:20 +00:00
|
|
|
struct resource_context {
|
|
|
|
struct pipe_ctx pipe_ctx[MAX_PIPES];
|
|
|
|
bool is_stream_enc_acquired[MAX_PIPES * 2];
|
|
|
|
bool is_audio_acquired[MAX_PIPES];
|
|
|
|
uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
|
|
|
|
uint8_t dp_clock_source_ref_count;
|
2019-02-22 20:54:43 +00:00
|
|
|
bool is_dsc_acquired[MAX_PIPES];
|
2021-09-02 14:01:02 +00:00
|
|
|
struct link_enc_cfg_context link_enc_cfg_ctx;
|
2021-06-09 19:21:35 +00:00
|
|
|
#if defined(CONFIG_DRM_AMD_DC_DCN)
|
|
|
|
bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS];
|
|
|
|
#endif
|
2020-11-02 20:37:34 +00:00
|
|
|
#if defined(CONFIG_DRM_AMD_DC_DCN)
|
2020-05-21 16:51:51 +00:00
|
|
|
bool is_mpc_3dlut_acquired[MAX_PIPES];
|
|
|
|
#endif
|
2017-05-02 21:29:48 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct dce_bw_output {
|
|
|
|
bool cpuc_state_change_enable;
|
|
|
|
bool cpup_state_change_enable;
|
|
|
|
bool stutter_mode_enable;
|
|
|
|
bool nbp_state_change_enable;
|
|
|
|
bool all_displays_in_sync;
|
|
|
|
struct dce_watermarks urgent_wm_ns[MAX_PIPES];
|
|
|
|
struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
|
2018-03-12 19:53:47 +00:00
|
|
|
struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
|
2017-05-02 21:29:48 +00:00
|
|
|
struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
|
|
|
|
int sclk_khz;
|
|
|
|
int sclk_deep_sleep_khz;
|
|
|
|
int yclk_khz;
|
|
|
|
int dispclk_khz;
|
|
|
|
int blackout_recovery_time_us;
|
|
|
|
};
|
|
|
|
|
2019-02-22 20:54:43 +00:00
|
|
|
struct dcn_bw_writeback {
|
|
|
|
struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
|
|
|
|
};
|
|
|
|
|
2017-05-02 21:29:48 +00:00
|
|
|
struct dcn_bw_output {
|
2018-05-23 22:02:27 +00:00
|
|
|
struct dc_clocks clk;
|
2017-05-02 21:29:48 +00:00
|
|
|
struct dcn_watermark_set watermarks;
|
2019-02-22 20:54:43 +00:00
|
|
|
struct dcn_bw_writeback bw_writeback;
|
2021-05-19 15:28:27 +00:00
|
|
|
int compbuf_size_kb;
|
2017-05-02 21:29:48 +00:00
|
|
|
};
|
|
|
|
|
2019-02-22 18:37:03 +00:00
|
|
|
union bw_output {
|
2017-05-02 21:29:48 +00:00
|
|
|
struct dcn_bw_output dcn;
|
|
|
|
struct dce_bw_output dce;
|
|
|
|
};
|
2017-09-12 19:58:20 +00:00
|
|
|
|
2019-02-22 18:37:03 +00:00
|
|
|
struct bw_context {
|
|
|
|
union bw_output bw;
|
|
|
|
struct display_mode_lib dml;
|
|
|
|
};
|
2018-10-09 13:45:28 +00:00
|
|
|
/**
|
|
|
|
* struct dc_state - The full description of a state requested by a user
|
|
|
|
*
|
|
|
|
* @streams: Stream properties
|
|
|
|
* @stream_status: The planes on a given stream
|
|
|
|
* @res_ctx: Persistent state of resources
|
2019-02-22 18:37:03 +00:00
|
|
|
* @bw_ctx: The output from bandwidth and watermark calculations and the DML
|
2018-10-09 13:45:28 +00:00
|
|
|
* @pp_display_cfg: PowerPlay clocks and settings
|
|
|
|
* @dcn_bw_vars: non-stack memory to support bandwidth calculations
|
|
|
|
*
|
|
|
|
*/
|
2017-08-25 20:16:10 +00:00
|
|
|
struct dc_state {
|
2017-07-27 13:33:33 +00:00
|
|
|
struct dc_stream_state *streams[MAX_PIPES];
|
2016-12-29 20:27:12 +00:00
|
|
|
struct dc_stream_status stream_status[MAX_PIPES];
|
|
|
|
uint8_t stream_count;
|
2020-08-21 21:15:36 +00:00
|
|
|
uint8_t stream_mask;
|
2017-09-12 19:58:20 +00:00
|
|
|
|
|
|
|
struct resource_context res_ctx;
|
|
|
|
|
2019-02-22 18:37:03 +00:00
|
|
|
struct bw_context bw_ctx;
|
2017-05-02 21:29:48 +00:00
|
|
|
|
2016-12-05 23:03:04 +00:00
|
|
|
/* Note: these are big structures, do *not* put on stack! */
|
2017-09-12 19:58:20 +00:00
|
|
|
struct dm_pp_display_configuration pp_display_cfg;
|
2019-11-06 19:48:35 +00:00
|
|
|
#ifdef CONFIG_DRM_AMD_DC_DCN
|
2017-06-15 20:27:42 +00:00
|
|
|
struct dcn_bw_internal_vars dcn_bw_vars;
|
|
|
|
#endif
|
2017-07-11 18:41:51 +00:00
|
|
|
|
2019-03-20 21:10:41 +00:00
|
|
|
struct clk_mgr *clk_mgr;
|
2017-08-28 18:25:01 +00:00
|
|
|
|
2017-10-03 02:39:02 +00:00
|
|
|
struct kref refcount;
|
2020-08-28 14:48:41 +00:00
|
|
|
|
|
|
|
struct {
|
|
|
|
unsigned int stutter_period_us;
|
|
|
|
} perf_params;
|
2017-09-12 19:58:20 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
#endif /* _CORE_TYPES_H_ */
|