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clk: at91: sam9x60-pll: use frac when setting frequency
In commita436c2a447
("clk: at91: add sam9x60 PLL driver") the fractional part of PLL wasn't set on registers but it was calculated and taken into account for determining div and mul (see sam9x60_pll_get_best_div_mul()). Fixes:a436c2a447
("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-7-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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390227dca8
commit
35d06f7478
1 changed files with 8 additions and 4 deletions
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@ -16,6 +16,7 @@
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#define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
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#define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)
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#define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
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#define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
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#define UPLL_DIV 2
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@ -55,7 +56,7 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
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unsigned long flags;
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u8 div;
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u16 mul;
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u32 val;
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u32 val, frac;
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spin_lock_irqsave(pll->lock, flags);
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regmap_write(regmap, AT91_PMC_PLL_UPDT, pll->id);
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@ -65,9 +66,10 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
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regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
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mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
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frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val);
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if (sam9x60_pll_ready(regmap, pll->id) &&
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(div == pll->div && mul == pll->mul)) {
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(div == pll->div && mul == pll->mul && frac == pll->frac)) {
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spin_unlock_irqrestore(pll->lock, flags);
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return 0;
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}
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@ -80,7 +82,8 @@ static int sam9x60_pll_prepare(struct clk_hw *hw)
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regmap_write(regmap, AT91_PMC_PLL_ACR, val);
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regmap_write(regmap, AT91_PMC_PLL_CTRL1,
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FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul));
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FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul) |
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FIELD_PREP(PMC_PLL_CTRL1_FRACR_MSK, pll->frac));
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if (pll->characteristics->upll) {
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/* Enable the UTMI internal bandgap */
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@ -155,7 +158,8 @@ static unsigned long sam9x60_pll_recalc_rate(struct clk_hw *hw,
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{
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struct sam9x60_pll *pll = to_sam9x60_pll(hw);
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return (parent_rate * (pll->mul + 1)) / (pll->div + 1);
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return DIV_ROUND_CLOSEST_ULL((parent_rate * (pll->mul + 1) +
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((u64)parent_rate * pll->frac >> 22)), (pll->div + 1));
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}
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static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
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