Commit graph

996211 commits

Author SHA1 Message Date
Sai Prakash Ranjan
0e51f883da arm64: dts: qcom: sc7280: Add APSS watchdog node
Add APSS (Application Processor Subsystem) watchdog
DT node for SC7280 SoC.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1615461961-17716-12-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:43 -06:00
Maulik Shah
e9d7397467 arm64: dts: qcom: sc7280: Add reserved memory for fw
Add fw reserved memory area for CPUCP (CPUSS control
processor) and AOP (Always ON processor)

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1615461961-17716-10-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:43 -06:00
Sai Prakash Ranjan
c73ed10440 arm64: dts: qcom: sc7280: Add device node for APPS SMMU
Adding device node for APPS SMMU available on SC7280 chipset.
This is shared among the multiple client devices such as
display, video, usb, mmc and others.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1615461961-17716-9-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:43 -06:00
Rajendra Nayak
ab7772de86 arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
Add rpmhcc clock controller node for SC7280. Also add references to
rpmhcc clocks in gcc.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1615461961-17716-7-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:43 -06:00
Maulik Shah
3450bb5b95 arm64: dts: qcom: sc7280: Add RSC and PDC devices
Add PDC interrupt controller along with apps RSC device.
Also add reserved memory for command_db.

Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1615461961-17716-6-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Rajendra Nayak
7a1f4e7f74 arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 soc
Add initial device tree support for the sc7280 SoC and the IDP
boards based on this SoC

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1615461961-17716-4-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Rajendra Nayak
36dc1681c9 dt-bindings: arm: qcom: Document sc7280 SoC and board
Document the sc7280 SoC and the IDP board bindings

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1615461961-17716-2-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Bjorn Andersson
9208c19f21 arm64: dts: qcom: Introduce SM8350 HDK
Add initial DTS for the Snapdragon 888 Mobile Hardware Development Kit,
aka SM8350 HDK. This initial version describes debug UART, UFS storage,
the three USB connectors and remoteprocs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210308182113.1284966-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Vinod Koul
9ad3c08f6f dt-bindings: arm: qcom: Document sony boards for apq8094
Document the various sony boards for apq8094. These are used in various
sony dts files but not documented

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210308060826.3074234-6-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Vinod Koul
c0dffc3fce arm64: dts: qcom: msm8994: don't use empty memory node
We expect bootloader to full memory details but passing empty values
gives warning, so add a default value

arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dt.yaml: /: memory:
	False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]}

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210308060826.3074234-5-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Vinod Koul
ddfb3fc482 dt-bindings: arm: qcom: Document ipq6018-cp01 board
Document the ipq6018-cp01 board. It was missing leading to warning:

arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: /: compatible: 'oneOf' conditional failed, one must be fixed:
        ['qcom,ipq6018-cp01', 'qcom,ipq6018'] is too short
        ['qcom,ipq6018-cp01', 'qcom,ipq6018'] is too long
        Additional items are not allowed ('qcom,ipq6018' was unexpected)

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210308060826.3074234-4-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Vinod Koul
74f417ca59 arm64: dts: qcom: msm8916: don't use empty memory node
We expect bootloader to full memory details but passing empty values
gives warning, so add a default value

arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: memory:
	False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]}

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210308060826.3074234-3-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Vinod Koul
acf050ab5d arm64: dts: qcom: apq8016-sbc: drop qcom,sbc
apq8016-sbc is one of the compaitibles for this board, but is not
documented, so drop it. This fixes these two warns:

arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc']
is not valid under any of the given schemas (Possible causes of the failure):

arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc'] is too long
arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc'
is not one of ['qcom,apq8064-cm-qs600', 'qcom,apq8064-ifc6410']
arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc'
is not one of ['qcom,apq8074-dragonboard']

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210308060826.3074234-2-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Douglas Anderson
e440e30e26 arm64: dts: qcom: sc7180: Avoid glitching SPI CS at bootup on trogdor
At boot time the following happens:
1. Device core gets ready to probe our SPI driver.
2. Device core applies SPI controller's "default" pinctrl.
3. Device core calls the SPI driver's probe() function which will
   eventually setup the chip select GPIO as "unasserted".

Thinking about the above, we can find:
a) For SPI devices that the BIOS inits (Cr50 and EC), the BIOS would
   have had them configured as "GENI" pins and not as "GPIO" pins.
b) It turns out that our BIOS also happens to init these pins as
   "output" (even though it doesn't need to since they're not muxed as
   GPIO) but leaves them at the default state of "low".
c) As soon as we apply the "default" chip select it'll switch the
   function to GPIO and stop driving the chip select high (which is
   how "GENI" was driving it) and start driving it low.
d) As of commit 9378f46040be ("UPSTREAM: spi: spi-geni-qcom: Use the
   new method of gpio CS control"), when the SPI core inits things it
   inits the GPIO to be "deasserted".  Prior to that commit the GPIO
   was left untouched until first use.
e) When the first transaction happens we'll assert the chip select and
   then deassert it after done.

So before the commit to change us to use gpio descriptors we used to
have a _really long_ assertion of chip select before our first
transaction (because it got pulled down and then the first "assert"
was a no-op).  That wasn't great but (apparently) didn't cause any
real harm.

After the commit to change us to use gpio descriptors we end up
glitching the chip select line during probe.  It would go low and then
high with no data transferred.  The other side ought to be robust
against this, but it certainly could cause some confusion.  It's known
to at least cause an error message on the EC console and it's believed
that, under certain timing conditions, it could be getting the EC into
a confused state causing the EC driver to fail to probe.

Let's fix things to avoid the glitch.  We'll add an extra pinctrl
entry that sets the value of the pin to output high (CS deasserted)
before doing anything else.  We'll do this in its own pinctrl node
that comes before the normal pinctrl entries to ensure that the order
is correct and that this gets applied before the mux change.

This change is in the trogdor board file rather than in the SoC dtsi
file because chip select polarity can be different depending on what's
hooked up and it doesn't feel worth it to spam the SoC dtsi file with
both options.  The board file would need to pick the right one anyway.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: cfbb97fde6 ("arm64: dts: qcom: Switch sc7180-trogdor to control SPI CS via GPIO")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210218145456.1.I1da01a075dd86e005152f993b2d5d82dd9686238@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Sandeep Maheswaram
1e6e6e7a08 arm64: dts: qcom: sc7180: Use pdc interrupts for USB instead of GIC interrupts
Using pdc interrupts for USB instead of GIC interrupts to
support wake up in case xo shutdown.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Link: https://lore.kernel.org/r/1594235417-23066-4-git-send-email-sanm@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:42 -06:00
Douglas Anderson
7d47b2cb1a arm64: dts: qcom: Add sc7180-trogdor-coachz skus
This is a trogdor variant.  This is mostly a grab from the downstream
tree with notable exceptions:
- I skip -rev0.  This was a super early build and there's no advantage
  of long term support.
- I remove sound node since sound hasn't landed upstream yet.

Cc: Gwendal Grignou <gwendal@chromium.org>
Cc: Matthias Kaehlcke <mka@chromium.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Tzung-Bi Shih <tzungbi@chromium.org>
Cc: Judy Hsiao <judyhsiao@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.13.I3d1f5f8a3bf31e8014229df0d4cfdff20e9cc90f@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Douglas Anderson
082607825a arm64: dts: qcom: Add sc7180-trogdor-pompom skus
This is a trogdor variant.  This is mostly a grab from the downstream
tree with notable exceptions:
- I skip -rev0.  This was a super early build and there's no advantage
  of long term support.
- In -rev1 I translate the handling of the USB hub like is done for
  similar boards.  See the difference between the downstream and
  upstream 'sc7180-trogdor-lazor-r0.dts' for an example.  This will
  need to be resolved when proper support for the USB hub is figured
  out upstream.
- I remove sound node since sound hasn't landed upstream yet.
- In incorporate the pending <https://crrev.com/c/2719075> for the
  keyboard.

Cc: Philip Chen <philipchen@google.com>
Cc: Matthias Kaehlcke <mka@chromium.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Tzung-Bi Shih <tzungbi@chromium.org>
Cc: Judy Hsiao <judyhsiao@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.12.If93a01b30d20dccacbad4be8ddc519dc20a51a1e@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Douglas Anderson
2c26adb8db arm64: dts: qcom: Add sc7180-lazor-limozeen skus
This is a SKU variant of lazor.  Add it.  This squashes the downstream
patches to support this hardware.

NOTES:
- The non-touch SKU actually has "innolux,n116bca-ea1" but that driver
  is still pending in simple-panel.  The bindings have been Acked
  though [1].  Things work well enough with the "innolux,n116bge"
  timings for now, though.
- The wonky special dts just for "-rev4" arguably doesn't need to go
  upstream since they weren't widely distributed, but since a few
  people have them we might as well.  If it ever causes problems we
  can delete it.

[1] https://lore.kernel.org/r/20210115144345.v2.4.I6889e21811df6adaff5c5b8a8c80fda0669ab3a5@changeid

Cc: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.11.I556326b24441e22c8c429ce383cc157c7aaef44b@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Matthias Kaehlcke
d1559628c2 arm64: dts: qcom: sc7180: Set up lazor r3+ as sc7180-lite SKUs
Lazor rev3 and later use the 'lite' version of the SC7180 SoC.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
[dianders: Adjust commit message which referred to downstream history]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.10.Ia3795e192f5bbe17e6714e45fcb0bf5acdbd4c17@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Abhishek Kumar
a4ebb84a09 arm64: dts: qcom: sc7180: add GO_LAZOR variant property for lazor
For trogdor, in the latest board-2.bin file, new BDF with variant
name GO_LAZOR has been introduced, so we need this property set, for
GO_LAZOR BDF to be picked.

Cc: Philip Chen <philipchen@chromium.org>
Signed-off-by: Abhishek Kumar <kuabhs@chromium.org>
[dianders: adjusted subject line and sort order]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.9.I4a38fe64dd79c54af80d7e4ef5940f8cf4f86e75@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Venkata Lakshmi Narayana Gubba
a307a97734 arm64: dts: qcom: sc7180: Remove clock for bluetooth on Trogdor
Removed voting for RPMH_RF_CLK2 which is not required as it is
getting managed by BT SoC through SW_CTRL line.

Cc: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.8.I80c268f163e6d49a70af1238be442b5de400c579@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Alexandru M Stan
1a5d8ff0d6 arm64: dts: qcom: sc7180-trogdor: Remove fp control pins in prep for coachz
Removed the pinctrl and pin{mux,conf} for the control pins because:
1. The only need for them is for userspace control via flash_fp_mcu
2. cros-ec doesn't know what to do with them, and even if it did,
   it would interfere with flash_fp_mcu at the most inopportune times

Since we're not using hogs, we rely on AP firmware to set all the
control pins correctly.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Craig Hesling <hesling@chromium.org>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
[dianders: adjusted since coachz isn't upstream yet]
Reviewed-by; Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.7.Ifd7b86f826b18410eada75758a7bca1eebfa336d@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Stephen Boyd
fcd66fe65d arm64: dts: qcom: Disable camera clk on sc7180-trogdor devices by default
We only want to use this clk driver on CoachZ devices. Disable it for
all other Trogdor boards.  NOTE: CoachZ devices aren't yet supported
upstream so until it is this is just disabled for all trogdor.

Cc: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
[dianders:adjusted since no coachz upstream yet]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.6.I22522b0c9db505ee43ed08e8d5d9e8fe632e7447@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Stephen Boyd
5643caa82e arm64: dts: qcom: trogdor: Only wakeup from pen eject
Configure the pen to be a wakeup source only when the pen is ejected
instead of both when the pen is ejected and inserted. This corresponds
to wake source requirements.

Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.5.Ib9672bfbe639c96c85408d6f0217a2609eb0b70f@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Douglas Anderson
f415e0f596 arm64: dts: qcom: Unify the sc7180-trogdor panel nodes
Let's avoid a bit of duplication by pushing this up to the trogdor.dtsi
file.

Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.4.I1483fac4c5ae4b2d7660290ff85d69945292618f@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Douglas Anderson
ce25002429 arm64: dts: qcom: Prep sc7180-trogdor trackpad IRQ for new boards
The trackpad interrupt got renamed and also moved to a new GPIO on
newer boards.  Let's do the move in the "trogdor.dtsi" file and then
undo it in the two old boards.

NOTE: since none of the new boards have device trees yet, this change
looks silly on its own but it will make sense after more boards are
supported.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.3.Iddf6dc8102aa4fbc3847936226fc7bf2e2cd315c@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:41 -06:00
Douglas Anderson
b4b2c20d62 arm64: dts: qcom: Move sc7180 MI2S config to board files and make pulldown
In general pinconf belongs in board files, not SoC files.  Move it to
the only current user (trogdor).  Also adjust the drive strengths and
pulls.

Cc: V Sujith Kumar Reddy <vsujithk@codeaurora.org>
Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Cc: Tzung-Bi Shih <tzungbi@chromium.org>
Cc: Judy Hsiao <judyhsiao@chromium.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.2.Id27e7e6f90c29bf623fa4880e18a14ba1dffd2d2@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Stephen Boyd
58fd7ae621 arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phy
Drop the old node and add the new one in its place.

Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
[dianders: Adjusted due to DP not itself not in upstream dts yet]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210301133318.v2.1.Iad06142ceb8426ce5492737bf3d9162ed0dd2b55@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
ccbb3abb23 arm64: dts: qcom: sm8350: Add cpufreq node
Add cpufreq node and reference it for the CPUs.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210216111703.1838663-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
6d91e20111 arm64: dts: qcom: sm8350: Use enums for GCC
Now that we have GCC define, use the enums instead of numbers in the DTS

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-8-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
da97c882a2 arm64: dts: qcom: sm8350-mtp: Enable remoteprocs
This enabled the four remoteprocs found in SM8350, audio, compute, modem
and sensor for MTP platform and adds firmware for them.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-7-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
177fcf0aed arm64: dts: qcom: sm8350: Add remoteprocs
Add remoteproc nodes for the audio, compute and sensor cores, define
glink for each one.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-6-vkoul@kernel.org
[bjorn: Replaced rpmhpd defines with constants, for now]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
03a41991d4 arm64: dts: qcom: sm8350: Add SMP2P nodes
SMP2P is used for interrupting and being interrupted about remoteproc
state changes related to the audio, compute, modem and sensor subsystems.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-5-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
774890c936 arm64: dts: qcom: sm8350: Add rmtfs node
Add the rmtfs as a reserved memory node.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-4-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
90f57509fe arm64: dts: qcom: sm8350: Add rpmhpd node
This adds RPMH power domain found in SM8350 SoC

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-3-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
4f23d2a557 arm64: dts: qcom: sm8350: fix typo
Fix the typo s/Limaited/Limited

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210212115532.1339942-2-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
2fc19af68a arm64: dts: qcom: sm8350-mtp: add regulator names
Add the property "regulator-names" to the regulators as given in
schematics so that it is easier to understand the regulators being used

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210204170907.63545-7-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
694103bc11 arm64: dts: qcom: sm8350-mtp: enable UFS nodes
Enabled the UFS node found in SM8350-MTP platform, also add the
regulators associated with UFS HC and UFS phy to these nodes.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210204170907.63545-6-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:40 -06:00
Vinod Koul
59c7cf8147 arm64: dts: qcom: sm8350: Add UFS nodes
This adds UFS HC and UFS phy nodes to the SM8350 DTS

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210204170907.63545-5-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Jack Pham
054b40a611 arm64: dts: qcom: sm8350-mtp: enable USB nodes
Enable both USB controllers and associated hsphy and qmp phy nodes
on sm8350 MTP. Designate the usb_1 instance as peripheral-mode only
until proper PMIC based Type-C dual-role handling is supported.

TODO: the second USB controller is exposed to a microAB port. Dual-
role can be supported for this by adding the "usb-role-switch"
property as well as defining a USB connector node with a
"gpio-usb-b-connector" compatible. However, this requires GPIO
support from PM8350 which is still missing.

Signed-off-by: Jack Pham <jackp@codeaurora.org>
Link: https://lore.kernel.org/r/20210116013802.1609-3-jackp@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210204170907.63545-4-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Jack Pham
e780fb318f arm64: dts: qcom: sm8350: add USB and PHY device nodes
Add device nodes for the two instances each of USB3 controllers,
QMP SS PHYs and SNPS HS PHYs.

Signed-off-by: Jack Pham <jackp@codeaurora.org>
Link: https://lore.kernel.org/r/20210116013802.1609-2-jackp@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210204170907.63545-3-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Vinod Koul
187f65b7f0 arm64: dts: qcom: sm8350: Add apss_smmu node
This adds apss_smmu node to SM8350 DTS

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210204170907.63545-2-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Sai Prakash Ranjan
29a3349543 arm64: dts: qcom: sm8250: Fix timer interrupt to specify EL2 physical timer
ARM architected timer interrupts DT property specifies EL2/HYP
physical interrupt and not EL2/HYP virtual interrupt for the 4th
interrupt property. As per interrupt documentation for SM8250 SoC,
the EL2/HYP physical timer interrupt is 10 and EL2/HYP virtual timer
interrupt is 12, so fix the 4th timer interrupt to be EL2 physical
timer interrupt (10 in this case).

Fixes: 60378f1a17 ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/744e58f725d279eb2b049a7da42b0f09189f4054.1613468366.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Sai Prakash Ranjan
794d3e309e arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity
As per interrupt documentation for SM8350 SoC, the polarity
for level triggered PMU interrupt is low, fix this.

Fixes: b7e8f433a6 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/ca57409198477f7815e32a6a7467dcdc9b93dc4f.1613468366.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Sai Prakash Ranjan
93138ef5ac arm64: dts: qcom: sm8250: Fix level triggered PMU interrupt polarity
As per interrupt documentation for SM8250 SoC, the polarity
for level triggered PMU interrupt is low, fix this.

Fixes: 60378f1a17 ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/96680a1c6488955c9eef7973c28026462b2a4ec0.1613468366.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Sai Prakash Ranjan
97832fa805 arm64: dts: qcom: sm8350: Rename the qmp node to power-controller
Use the generic DT node name "power-controller" for AOSS message ram
instead of the protocol name QMP(Qualcomm Messaging Protocol) since
it is used for power management requests.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/15005f1441594670adcd60a300c88e41d79cad27.1614669585.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Sai Prakash Ranjan
43f14a0b4f arm64: dts: qcom: sm8250: Rename the qmp node to power-controller
Use the generic DT node name "power-controller" for AOSS message ram
instead of the protocol name QMP(Qualcomm Messaging Protocol) since
it is used for power management requests.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/044fe2e590e166060de65f074df6874ec3a79531.1614669585.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Sai Prakash Ranjan
f81c1e518f arm64: dts: qcom: sdm845: Rename the qmp node to power-controller
Use the generic DT node name "power-controller" for AOSS message ram
instead of the protocol name QMP(Qualcomm Messaging Protocol) since
it is used for power management requests.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/55416e116dda4aad977bb050451d328b1f6b00d3.1614669585.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Sai Prakash Ranjan
26d06feace arm64: dts: qcom: sc7180: Rename the qmp node to power-controller
Use the generic DT node name "power-controller" for AOSS message ram
instead of the protocol name QMP(Qualcomm Messaging Protocol) since
it is used for power management requests.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/e96d665d1e98b46a189a57e39575ae0debf37172.1614669585.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:39 -06:00
Matthias Kaehlcke
e4ffe8d5f0 arm64: dts: qcom: sc7180: trogdor: Use ADC TM channel 0 instead of 1 for charger temperature
On trogdor the ADC thermal monitor is used for monitoring certain
device temperatures. All trogdor boards have at least a thermistor
for the charger temperature, optionally they may have others.

Currently the ADC thermal monitor is configured to use channel 1
for the charger temperature. Given that all trogdor boards have
the charger thermistor it makes more sense to use channel 0,
and then let boards with other thermistors use channels 1, 2, 3,
rather than 0, 2, 3.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20210225103330.v2.4.I67e29f2854bad22e3581d6a6e1879b9fc8abbdea@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11 20:22:38 -06:00