Commit graph

6378 commits

Author SHA1 Message Date
Andy Shevchenko
62140a1e4d Revert "pinctrl: avoid unsafe code pattern in find_pinctrl()"
The commit breaks MMC enumeration on the Intel Merrifield
plaform.

Before:
[   36.439057] mmc0: SDHCI controller on PCI [0000:00:01.0] using ADMA
[   36.450924] mmc2: SDHCI controller on PCI [0000:00:01.3] using ADMA
[   36.459355] mmc1: SDHCI controller on PCI [0000:00:01.2] using ADMA
[   36.706399] mmc0: new DDR MMC card at address 0001
[   37.058972] mmc2: new ultra high speed DDR50 SDIO card at address 0001
[   37.278977] mmcblk0: mmc0:0001 H4G1d 3.64 GiB
[   37.297300]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10

After:
[   36.436704] mmc2: SDHCI controller on PCI [0000:00:01.3] using ADMA
[   36.436720] mmc1: SDHCI controller on PCI [0000:00:01.0] using ADMA
[   36.463685] mmc0: SDHCI controller on PCI [0000:00:01.2] using ADMA
[   36.720627] mmc1: new DDR MMC card at address 0001
[   37.068181] mmc2: new ultra high speed DDR50 SDIO card at address 0001
[   37.279998] mmcblk1: mmc1:0001 H4G1d 3.64 GiB
[   37.302670]  mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10

This reverts commit c153a4edff.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20231017141806.535191-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-19 10:12:48 +02:00
Krzysztof Kozlowski
c8befdc411 pinctrl: qcom: lpass-lpi: fix concurrent register updates
The Qualcomm LPASS LPI pin controller driver uses one lock for guarding
Read-Modify-Write code for slew rate registers.  However the pin
configuration and muxing registers have exactly the same RMW code but
are not protected.

Pin controller framework does not provide locking here, thus it is
possible to trigger simultaneous change of pin configuration registers
resulting in non-atomic changes.

Protect from concurrent access by re-using the same lock used to cover
the slew rate register.  Using the same lock instead of adding second
one will make more sense, once we add support for newer Qualcomm SoC,
where slew rate is configured in the same register as pin
configuration/muxing.

Fixes: 6e261d1090 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver")
Cc: stable@vger.kernel.org
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231013145705.219954-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-16 14:56:49 +02:00
Ralph Siemsen
f055ff23c3 pinctrl: renesas: rzn1: Enable missing PINMUX
Enable pin muxing (eg. programmable function), so that the RZ/N1 GPIO
pins will be configured as specified by the pinmux in the DTS.

This used to be enabled implicitly via CONFIG_GENERIC_PINMUX_FUNCTIONS,
however that was removed, since the RZ/N1 driver does not call any of
the generic pinmux functions.

Fixes: 1308fb4e4e ("pinctrl: rzn1: Do not select GENERIC_PIN{CTRL_GROUPS,MUX_FUNCTIONS}")
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231004200008.1306798-1-ralph.siemsen@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-10-12 09:10:40 +02:00
Linus Walleij
8be586f78d Revert "pinctrl: tegra: Add support to display pin function"
This reverts commit d1cd5b51bc.

It was reported that some I2C3 functions stop working after this
patch, and it is just debug help so let's revert it and investigate.

Link: https://lore.kernel.org/linux-gpio/20230925183049.10a40546@booty/
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-27 10:51:57 +02:00
Dmitry Torokhov
c153a4edff pinctrl: avoid unsafe code pattern in find_pinctrl()
The code in find_pinctrl() takes a mutex and traverses a list of pinctrl
structures. Later the caller bumps up reference count on the found
structure. Such pattern is not safe as pinctrl that was found may get
deleted before the caller gets around to increasing the reference count.

Fix this by taking the reference count in find_pinctrl(), while it still
holds the mutex.

Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Link: https://lore.kernel.org/r/ZQs1RgTKg6VJqmPs@google.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-25 15:29:26 +02:00
Hal Feng
64061b6733 pinctrl: starfive: jh7110: Add system pm ops to save and restore context
Add system pm ops to save and restore pinctrl registers
when suspending and resuming the driver, respectively.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Link: https://lore.kernel.org/r/20230905122105.117000-3-hal.feng@starfivetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-12 10:09:40 +02:00
Hal Feng
8406d6b591 pinctrl: starfive: jh7110: Fix failure to set irq after CONFIG_PM is enabled
The issue was found when we enabled CONFIG_PM and tested edge events using
libgpiod.

> # gpiomon -r gpiochip0 55
> gpiomon: error waiting for events: Permission denied

`gpiomon` will call irq_chip_pm_get() and then call pm_runtime_resume_and_get()
if (IS_ENABLED(CONFIG_PM) && sfp->gc.irq.domain->pm_dev).
pm_runtime_resume_and_get() will fail if the runtime pm of pinctrl device
is disabled.

As we expect the pinctrl driver can be always working and never suspend
during runtime, unset sfp->gc.irq.domain->pm_dev to make sure
pm_runtime_resume_and_get() won't be called when setting irq.

Fixes: 447976ab62 ("pinctrl: starfive: Add StarFive JH7110 sys controller driver")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Link: https://lore.kernel.org/r/20230905122105.117000-2-hal.feng@starfivetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-12 10:09:40 +02:00
Mikhail Kobuk
87d315a341 pinctrl: nuvoton: wpcm450: fix out of bounds write
Write into 'pctrl->gpio_bank' happens before the check for GPIO index
validity, so out of bounds write may happen.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Fixes: a1d1e0e3d8 ("pinctrl: nuvoton: Add driver for WPCM450")
Signed-off-by: Mikhail Kobuk <m.kobuk@ispras.ru>
Reviewed-by: Alexey Khoroshilov <khoroshilov@ispras.ru>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20230825101532.6624-1-m.kobuk@ispras.ru
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-12 09:03:18 +02:00
YueHaibing
00078e834e pinctrl: lantiq: Remove unsued declaration ltq_pinctrl_unregister()
Commit 3f8c50c9b1 ("OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support")
declared but never implemented it, so can be removed.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20230825092706.14680-1-yuehaibing@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-09-11 15:42:12 +02:00
Linus Torvalds
4a3b1007ee Pin control bulk changes for the v6.6 kernel cycle:
No core changes this time.
 
 Drivers:
 
 - Intel Tangier SoC pin control support.
 
 - AMLogic C3 SoC pin control support.
 
 - Texas Instruments AM654 SoC pin control support.
 
 - Qualcomm SM8350 and SM6115 LPASS (Low Power Audio Sub-System)
   pin control support.
 
 - Qualcomm PMX75 and PM7550BA (Power Management) pin control
   support.
 
 - Qualcomm PMC8180 and PMC8180C (Power Management) pin control
   support.
 
 - DROP the Oxnas driver as there is not enough of community
   interest to keep carrying this ARM(11) port.
 
 Enhancements:
 
 - Bias control in the MT7986 pin control driver.
 
 - Misc device tree binding enhancements such as the Broadcom
   11351 being converted to YAML.
 
 - New macro: DEFINE_NOIRQ_DEV_PM_OPS() put to use.
 
 - Clean up some SPDX headers.
 
 - Handle non-unique devicetree subnode names in two Renesas
   drivers.
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Merge tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "We have some patches to DTS[I] files in arm and arm64 as well, that
  were merged here as DT headers were being changed.

  The most interesting stuff is the Intel Tangier chip support and
  AMLogic C3 in my opinion.

  No core changes this time.

  Drivers:

   - Intel Tangier SoC pin control support

   - AMLogic C3 SoC pin control support

   - Texas Instruments AM654 SoC pin control support

   - Qualcomm SM8350 and SM6115 LPASS (Low Power Audio Sub-System) pin
     control support

   - Qualcomm PMX75 and PM7550BA (Power Management) pin control support

   - Qualcomm PMC8180 and PMC8180C (Power Management) pin control
     support

   - DROP the Oxnas driver as there is not enough of community interest
     to keep carrying this ARM(11) port

  Enhancements:

   - Bias control in the MT7986 pin control driver

   - Misc device tree binding enhancements such as the Broadcom 11351
     being converted to YAML

   - New macro: DEFINE_NOIRQ_DEV_PM_OPS() put to use

   - Clean up some SPDX headers

   - Handle non-unique devicetree subnode names in two Renesas drivers"

* tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
  pinctrl: mlxbf3: Remove gpio_disable_free()
  pinctrl: use capital "OR" for multiple licenses in SPDX
  dt-bindings: pinctrl: renesas,rza2: Use 'additionalProperties' for child nodes
  pinctrl: cherryview: fix address_space_handler() argument
  pinctrl: intel: consolidate ACPI dependency
  pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: mvebu: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: at91: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pm: Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: mediatek: assign functions to configure pin bias on MT7986
  pinctrl: mediatek: fix pull_type data for MT7981
  dt-bindings: pinctrl: aspeed: Allow only defined pin mux node properties
  dt-bindings: pinctrl: Drop 'phandle' properties
  pinctrl: lynxpoint: Make use of pm_ptr()
  pinctrl: baytrail: Make use of pm_ptr()
  pinctrl: intel: Switch to use exported namespace
  pinctrl: lynxpoint: reuse common functions from pinctrl-intel
  pinctrl: cherryview: reuse common functions from pinctrl-intel
  ...
2023-08-30 19:36:19 -07:00
Linus Torvalds
3b6bf5b1f8 spi: Updates for v6.6
There's been quite a lot of generic activity here, but more
 administrative than featuers.  We also have a bunch of new drivers,
 including one that's part of a MFD so we pulled in the core parts of
 that:
 
  - Lots of work from both Yang Yingliang and Andy Shevchenko on moving
    to host/device/controller based terminology for devices.
  - QuadSPI SPI support for Allwinner sun6i.
  - New device support Cirrus Logic CS43L43, Longsoon, Qualcomm GENI
    QuPv3 and StarFive JH7110 QSPI.
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Merge tag 'spi-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "There's been quite a lot of generic activity here, but more
  administrative than featuers. We also have a bunch of new drivers,
  including one that's part of a MFD so we pulled in the core parts of
  that:

   - Lots of work from both Yang Yingliang and Andy Shevchenko on moving
     to host/device/controller based terminology for devices.

   - QuadSPI SPI support for Allwinner sun6i.

   - New device support Cirrus Logic CS43L43, Longsoon, Qualcomm GENI
     QuPv3 and StarFive JH7110 QSPI"

* tag 'spi-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (151 commits)
  spi: at91-usart: Use PTR_ERR_OR_ZERO() to simplify code
  spi: spi-sn-f-ospi: switch to use modern name
  spi: sifive: switch to use modern name
  spi: sh: switch to use modern name
  spi: sh-sci: switch to use modern name
  spi: sh-msiof: switch to use modern name
  spi: sh-hspi: switch to use modern name
  spi: sc18is602: switch to use modern name
  spi: s3c64xx: switch to use modern name
  spi: rzv2m-csi: switch to use devm_spi_alloc_host()
  spi: rspi: switch to use spi_alloc_host()
  spi: rockchip: switch to use modern name
  spi: rockchip-sfc: switch to use modern name
  spi: realtek-rtl: switch to use devm_spi_alloc_host()
  spi: rb4xx: switch to use modern name
  spi: qup: switch to use modern name
  spi: spi-qcom-qspi: switch to use modern name
  spi: pxa2xx: switch to use modern name
  spi: ppc4xx: switch to use modern name
  spi: spl022: switch to use modern name
  ...
2023-08-29 09:47:33 -07:00
Linus Walleij
82a65f0844 intel-pinctrl for v6.6-1
* New library driver for Intel MID to deduplicate code (Raag Jadav)
 * Reuse common functions from pinctrl-intel to reduce the code (Raag Jadav)
 * Move most of the exported functions to the PINCTRL_INTEL namespace
 * Make use of pm_ptr() in Bay Trail and Lynxpoint drivers
 * Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper and use it in a few drivers
 * Consolidata ACPI dependency in Kconfig (Raag Jadav)
 * Fix address_space_handler() argument in Cherryview driver (Raag Jadav)
 * Optinmize byt_pin_config_set() to avoid IO in error cases (Raag Jadav)
 
 The following is an automated git shortlog grouped by driver:
 
 at91:
  -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
 
 baytrail:
  -  Make use of pm_ptr()
  -  reuse common functions from pinctrl-intel
  -  consolidate common mask operation
 
 cherryview:
  -  fix address_space_handler() argument
  -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  -  reuse common functions from pinctrl-intel
 
 intel:
  -  consolidate ACPI dependency
  -  Switch to use exported namespace
  -  export common pinctrl functions
 
 lynxpoint:
  -  Make use of pm_ptr()
  -  reuse common functions from pinctrl-intel
 
 Merge patch series:
  - Merge patch series "Introduce Intel Tangier pinctrl driver"
  - Merge patch series "Reuse common functions from pinctrl-intel"
 
 merrifield:
  -  Adapt to Intel Tangier driver
 
 moorefield:
  -  Adapt to Intel Tangier driver
 
 mvebu:
  -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
 
 pm:
  -  Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper
 
 renesas:
  -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
 
 tangier:
  -  Introduce Intel Tangier driver
 
 tegra:
  -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
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Merge tag 'intel-pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel

intel-pinctrl for v6.6-1

* New library driver for Intel MID to deduplicate code (Raag Jadav)
* Reuse common functions from pinctrl-intel to reduce the code (Raag Jadav)
* Move most of the exported functions to the PINCTRL_INTEL namespace
* Make use of pm_ptr() in Bay Trail and Lynxpoint drivers
* Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper and use it in a few drivers
* Consolidata ACPI dependency in Kconfig (Raag Jadav)
* Fix address_space_handler() argument in Cherryview driver (Raag Jadav)
* Optinmize byt_pin_config_set() to avoid IO in error cases (Raag Jadav)

The following is an automated git shortlog grouped by driver:

at91:
 -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper

baytrail:
 -  Make use of pm_ptr()
 -  reuse common functions from pinctrl-intel
 -  consolidate common mask operation

cherryview:
 -  fix address_space_handler() argument
 -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
 -  reuse common functions from pinctrl-intel

intel:
 -  consolidate ACPI dependency
 -  Switch to use exported namespace
 -  export common pinctrl functions

lynxpoint:
 -  Make use of pm_ptr()
 -  reuse common functions from pinctrl-intel

Merge patch series:
 - Merge patch series "Introduce Intel Tangier pinctrl driver"
 - Merge patch series "Reuse common functions from pinctrl-intel"

merrifield:
 -  Adapt to Intel Tangier driver

moorefield:
 -  Adapt to Intel Tangier driver

mvebu:
 -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper

pm:
 -  Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper

renesas:
 -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper

tangier:
 -  Introduce Intel Tangier driver

tegra:
 -  Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-25 15:47:18 +02:00
Asmaa Mnebhi
69657e60b8 pinctrl: mlxbf3: Remove gpio_disable_free()
Remove support for gpio_disable_free() because it is called when the libgpiod
command "gpioset" is invoked. This gives the GPIO control back to hardware which
cancels out the effort to set the GPIO value.

Reminder of the code flow to change a GPIO value from software:
1) All GPIOs are controlled by hardware by default
2) To change the GPIO value, enable software control via a mux.
3) Once software has control over the GPIO pin, the gpio-mlxbf3 driver
   will be able to change the direction and value of the GPIO.

When the user runs "gpioset gpiochip0 0=0" for example, the gpio
pin value should change from 1 to 0. In this case, mlxbf3_gpio_request_enable()
is called via gpiochip_generic_request(). The latter switches GPIO control from
hardware to software. Then the GPIO value is changed from 1 to 0. However,
gpio_disable_free() is also called which changes control back to hardware
which changes the GPIO value back to 1.

Fixes: d11f932808 ("pinctrl: mlxbf3: Add pinctrl driver support")
Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230818164314.8505-2-asmaa@nvidia.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-25 15:44:15 +02:00
Krzysztof Kozlowski
c0f84760b0 pinctrl: use capital "OR" for multiple licenses in SPDX
Documentation/process/license-rules.rst and checkpatch expect the SPDX
identifier syntax for multiple licenses to use capital "OR".  Correct it
to keep consistent format and avoid copy-paste issues.

Correct also the placement of SPDX identifier in pinctrl-meson-axg
files:

  WARNING: Misplaced SPDX-License-Identifier tag - use line 1 instead

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230823085546.116494-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-23 14:31:58 +02:00
Raag Jadav
d5301c9071 pinctrl: cherryview: fix address_space_handler() argument
First argument of acpi_*_address_space_handler() APIs is acpi_handle of
the device, which is incorrectly passed in driver ->remove() path here.
Fix it by passing the appropriate argument and while at it, make both
API calls consistent using ACPI_HANDLE().

Fixes: a0b028597d ("pinctrl: cherryview: Add support for GMMR GPIO opregion")
Cc: stable@vger.kernel.org
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-22 14:51:10 +03:00
Raag Jadav
da41309b61 pinctrl: intel: consolidate ACPI dependency
Since all the Intel specific platform drivers depend on ACPI, we can
consolidate their config dependency.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-22 14:47:42 +03:00
Andy Shevchenko
83f7586f3b pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
Since pm.h provides a helper for system no-IRQ PM callbacks,
switch the driver to use it instead of open coded variant.

With that, make sure the PM ops are used only in CONFIG_PM_SLEEP=y
case by wrapping them in pm_sleep_ptr() macro.

Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20230717172821.62827-11-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21 19:07:44 +03:00
Andy Shevchenko
727eb02eb7 pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
Since pm.h provides a helper for system no-IRQ PM callbacks,
switch the driver to use it instead of open coded variant.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230717172821.62827-10-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21 19:00:18 +03:00
Andy Shevchenko
c9008b71be pinctrl: mvebu: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
Since pm.h provides a helper for system no-IRQ PM callbacks,
switch the driver to use it instead of open coded variant.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20230717172821.62827-9-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21 18:58:10 +03:00
Andy Shevchenko
f0d8d0eea5 pinctrl: at91: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
Since pm.h provides a helper for system no-IRQ PM callbacks,
switch the driver to use it instead of open coded variant.

With that switch pm_ptr() to pm_sleep_ptr() as the above
mentioned callbacks are only used for system sleep.

The use of the pm_sleep_ptr() macro allows the compiler
to always see the dev_pm_ops structure and related functions,
while still allowing the unused code to be removed, without
the need for the __maybe_unused markings.

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230717172821.62827-7-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21 18:58:10 +03:00
Andy Shevchenko
e5f32bf097 pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
Since pm.h provides a helper for system no-IRQ PM callbacks,
switch the driver to use it instead of open coded variant.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230717172821.62827-4-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-21 18:58:10 +03:00
Daniel Golle
0d8387fba9 pinctrl: mediatek: assign functions to configure pin bias on MT7986
Assign bias_disable_get/set and bias_get/set functions to allow
configuring pin bias on MT7986.

Fixes: 2c58d8dc9c ("pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/47f72372354312a839b9337e09476aadcc206e8b.1692327317.git.daniel@makrotopia.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-21 12:39:11 +02:00
Daniel Golle
8f6f16fe15 pinctrl: mediatek: fix pull_type data for MT7981
MediaTek has released pull_type data for MT7981 in their SDK.
Use it and set functions to configure pin bias.

Fixes: 6c83b2d94f ("pinctrl: add mt7981 pinctrl driver")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/7bcc8ead25dbfabc7f5a85d066224a926fbb4941.1692327317.git.daniel@makrotopia.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-21 12:39:11 +02:00
Mario Limonciello
6bc3462a0f pinctrl: amd: Mask wake bits on probe again
Shubhra reports that their laptop is heating up over s2idle. Even though
it's getting into the deepest state, it appears to be having spurious
wakeup events.

While debugging a tangential issue with the RTC Carsten reports that recent
6.1.y based kernel face a similar problem.

Looking at acpidump and GPIO register comparisons these spurious wakeup
events are from the GPIO associated with the I2C touchpad on both laptops
and occur even when the touchpad is not marked as a wake source by the
kernel.

This means that the boot firmware has programmed these bits and because
Linux didn't touch them lead to spurious wakeup events from that GPIO.

To fix this issue, restore most of the code that previously would clear all
the bits associated with wakeup sources. This will allow the kernel to only
program the wake up sources that are necessary.

This is similar to what was done previously; but only the wake bits are
cleared by default instead of interrupts and wake bits.  If any other
problems are reported then it may make sense to clear interrupts again too.

Cc: Sachi King <nakato@nakato.io>
Cc: stable@vger.kernel.org
Cc: Thorsten Leemhuis <regressions@leemhuis.info>
Fixes: 65f6c7c91c ("pinctrl: amd: Revert "pinctrl: amd: disable and mask interrupts on probe"")
Reported-by: Shubhra Prakash Nandi <email2shubhra@gmail.com>
Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217754
Reported-by: Carsten Hatger <xmb8dsv4@gmail.com>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=217626#c28
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20230818144850.1439-1-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-21 12:28:28 +02:00
Linus Walleij
6046c356ad pinctrl: renesas: Fixes for v6.5 (take two)
- Fix race conditions in pinctrl group and function creation/remove
     calls on the RZ/G2L, RZ/V2M, and RZ/A2 SoC families.
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Merge tag 'renesas-pinctrl-fixes-for-v6.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into fixes

pinctrl: renesas: Fixes for v6.5 (take two)

  - Fix race conditions in pinctrl group and function creation/remove
    calls on the RZ/G2L, RZ/V2M, and RZ/A2 SoC families.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-21 12:24:33 +02:00
Andy Shevchenko
1956149dec pinctrl: lynxpoint: Make use of pm_ptr()
Cleaning up the driver to use pm_ptr() and *_PM_OPS() macros that
make it simpler and allows the compiler to remove those functions
if built without CONFIG_PM and CONFIG_PM_SLEEP support.

The lp_gpio_resume() is also assigned to .thaw and .restore members.
This is not a problem as the function it enables input pins that
had been disabled by firmware and repetion of that doesn't change
the pin configuration, i.e. it is idempotent.

Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20230717172821.62827-6-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-18 19:42:37 +03:00
Mark Brown
038e0da7ba Immutable branch between MFD, Pinctrl and soundwire due for the v6.6 merge window
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mfd: Immutable branch between MFD, Pinctrl and soundwire due for the v6.6 merge window

Merge tag 'ib-mfd-pinctrl-soundwire-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into tmp

Immutable branch between MFD, Pinctrl and soundwire due for the v6.6 merge window
2023-08-18 17:37:08 +01:00
Andy Shevchenko
df660f66ba pinctrl: baytrail: Make use of pm_ptr()
Cleaning up the driver to use pm_ptr() and *_PM_OPS() macros that
make it simpler and allows the compiler to remove those functions
if built without CONFIG_PM and CONFIG_PM_SLEEP support.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20230717172821.62827-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-18 19:35:28 +03:00
Biju Das
8fcc1c40b7 pinctrl: renesas: rza2: Add lock around pinctrl_generic{{add,remove}_group,{add,remove}_function}
The pinctrl group and function creation/remove calls expect
caller to take care of locking. Add lock around these functions.

Fixes: b59d0e7827 ("pinctrl: Add RZ/A2 pin and gpio controller")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230815131558.33787-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-08-18 13:01:41 +02:00
Biju Das
f982b9d57e pinctrl: renesas: rzv2m: Fix NULL pointer dereference in rzv2m_dt_subnode_to_map()
Fix the below random NULL pointer crash during boot by serializing
pinctrl group and function creation/remove calls in
rzv2m_dt_subnode_to_map() with mutex lock.

Crash logs:
    pc : __pi_strcmp+0x20/0x140
    lr : pinmux_func_name_to_selector+0x68/0xa4
    Call trace:
    __pi_strcmp+0x20/0x140
    pinmux_generic_add_function+0x34/0xcc
    rzv2m_dt_subnode_to_map+0x2e4/0x418
    rzv2m_dt_node_to_map+0x15c/0x18c
    pinctrl_dt_to_map+0x218/0x37c
    create_pinctrl+0x70/0x3d8

While at it, add a comment for lock.

Fixes: 92a9b82525 ("pinctrl: renesas: Add RZ/V2M pin and gpio controller driver")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230815131558.33787-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-08-18 13:01:41 +02:00
Biju Das
661efa2284 pinctrl: renesas: rzg2l: Fix NULL pointer dereference in rzg2l_dt_subnode_to_map()
Fix the below random NULL pointer crash during boot by serializing
pinctrl group and function creation/remove calls in
rzg2l_dt_subnode_to_map() with mutex lock.

Crash log:
    pc : __pi_strcmp+0x20/0x140
    lr : pinmux_func_name_to_selector+0x68/0xa4
    Call trace:
    __pi_strcmp+0x20/0x140
    pinmux_generic_add_function+0x34/0xcc
    rzg2l_dt_subnode_to_map+0x314/0x44c
    rzg2l_dt_node_to_map+0x164/0x194
    pinctrl_dt_to_map+0x218/0x37c
    create_pinctrl+0x70/0x3d8

While at it, add comments for bitmap_lock and lock.

Fixes: c4c4637eb5 ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver")
Tested-by: Chris Paterson <Chris.Paterson2@renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230815131558.33787-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-08-18 13:01:41 +02:00
Charles Keepax
d5282a5392 pinctrl: cs42l43: Add support for the cs42l43
The CS42L43 is an audio CODEC with integrated MIPI SoundWire interface
(Version 1.2.1 compliant), I2C, SPI, and I2S/TDM interfaces designed
for portable applications. It provides a high dynamic range, stereo
DAC for headphone output, two integrated Class D amplifiers for
loudspeakers, and two ADCs for wired headset microphone input or
stereo line input. PDM inputs are provided for digital microphones.

Add a basic pinctrl driver which supports driver strength for the
various pins, gpios, and pinmux for the 2 multi-function pins.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20230804104602.395892-5-ckeepax@opensource.cirrus.com
Signed-off-by: Lee Jones <lee@kernel.org>
2023-08-17 12:06:11 +01:00
Andy Shevchenko
34393c3678 pinctrl: intel: Switch to use exported namespace
We already have a few symbols exported in the namespace.
Let's do the same for others (except PM for now).

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 19:21:38 +03:00
Andy Shevchenko
563532b49a Merge patch series "Reuse common functions from pinctrl-intel"
Raag Jadav <raag.jadav@intel.com> says:

This series exports common pinctrl functions that are used across
Intel specific platform drivers to PINCTRL_INTEL namespace and
reuses them into Baytrail, Cherryview and Lynxpoint drivers.
This helps reduce their code and memory footprint.

X86 kernels are fairly unikernels such that pinctrl-intel driver is
enabled by most Linux distributions and most Intel specific platform
drivers (inside drivers/pinctrl/intel) depend on it.

The only exception to this is Lynxpoint. But taking into account its
fairly old age, it wouldn't suffer much from pinctrl-intel dependency.

bloat-o-meter:
==============

Intel:
add/remove: 17/10 grow/shrink: 0/0 up/down: 375/-319 (56)
Total: Before=9598, After=9654, chg +0.58%

Baytrail:
add/remove: 1/6 grow/shrink: 0/2 up/down: 41/-441 (-400)
Total: Before=16538, After=16138, chg -2.42%

Cherryview:
add/remove: 1/6 grow/shrink: 2/0 up/down: 90/-272 (-182)
Total: Before=18133, After=17951, chg -1.00%

Lynxpoint:
add/remove: 1/6 grow/shrink: 0/1 up/down: 24/-354 (-330)
Total: Before=7836, After=7506, chg -4.21%

Link: https://lore.kernel.org/r/20230814060311.15945-1-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 17:34:11 +03:00
Raag Jadav
976cf4a6ee pinctrl: lynxpoint: reuse common functions from pinctrl-intel
Reuse common functions from pinctrl-intel driver.
While at it, select pinctrl-intel for Intel Lynxpoint driver.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230814060311.15945-5-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 17:33:42 +03:00
Raag Jadav
a2118cebc6 pinctrl: cherryview: reuse common functions from pinctrl-intel
Reuse common functions from pinctrl-intel driver.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230814060311.15945-4-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 17:33:42 +03:00
Raag Jadav
4d01688fdf pinctrl: baytrail: reuse common functions from pinctrl-intel
Reuse common functions from pinctrl-intel driver.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230814060311.15945-3-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 17:33:42 +03:00
Raag Jadav
25018ace79 pinctrl: intel: export common pinctrl functions
Export common pinctrl functions that are used across Intel specific
platform drivers, so that they can be reused.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Link: https://lore.kernel.org/r/20230814060311.15945-2-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 17:33:42 +03:00
Andy Shevchenko
e4e1718672 Merge patch series "Introduce Intel Tangier pinctrl driver"
Raag Jadav <raag.jadav@intel.com> says:

Merrifield and Moorefield pinctrl driver implementations are similar
in terms of how they access the hardware. We can consolidate their
pinctrl functionalities into a common library driver.

This patch set introduces:

1. Intel Tangier driver that supports the common pinctrl functionalities
   for Merrifield and Moorefield platforms.

2. Intel Tangier adaptation for Merrifield pinctrl driver.

3. Intel Tangier adaptation for Moorefield pinctrl driver.

Tested on Intel Edison platform.
No deviation observed in the contents of below entries before and after
this patchset.

- /proc/interrupts
- /sys/kernel/debug/gpio
- /sys/kernel/debug/pinctrl/*/pins

Link: https://lore.kernel.org/r/20230814054033.12004-1-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 17:32:21 +03:00
Raag Jadav
8574e4d994 pinctrl: moorefield: Adapt to Intel Tangier driver
Make use of Intel Tangier as a library driver for Moorefield.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Link: https://lore.kernel.org/r/20230814054033.12004-4-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 17:31:50 +03:00
Raag Jadav
4e1edcc7a9 pinctrl: merrifield: Adapt to Intel Tangier driver
Make use of Intel Tangier as a library driver for Merrifield.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Link: https://lore.kernel.org/r/20230814054033.12004-3-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 17:31:50 +03:00
Raag Jadav
79433559d2 pinctrl: tangier: Introduce Intel Tangier driver
Intel Tangier implements the common pinctrl functionalities for
Merrifield and Moorefield platforms.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Link: https://lore.kernel.org/r/20230814054033.12004-2-raag.jadav@intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 17:31:50 +03:00
Raag Jadav
4cfff5b7af pinctrl: baytrail: consolidate common mask operation
Consolidate common mask operation outside of switch cases and
limit IO operations to positive cases.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-08-15 16:06:26 +03:00
Linus Walleij
cd40a1ffdd Qualcomm pinctrl changes for v6.6
1. Add support for the SM6115 and SM8350 LPASS (Low Power Audio
    SubSystem) TLMM pin controllers.
 
 2. Add bindings for the Qualcomm PMC8180 and PMC8180C PMICs GPIO pin
    controllers.
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Merge tag 'qcom-pinctrl-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel

Qualcomm pinctrl changes for v6.6

1. Add support for the SM6115 and SM8350 LPASS (Low Power Audio
   SubSystem) TLMM pin controllers.

2. Add bindings for the Qualcomm PMC8180 and PMC8180C PMICs GPIO pin
   controllers.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-15 11:09:06 +02:00
Neil Armstrong
e693b6a896 pinctrl: pinctrl-oxnas: remove obsolete pinctrl driver
Due to lack of maintenance and stall of development for a few years now,
and since no new features will ever be added upstream, remove support
for OX810 and OX820 pinctrl & gpio.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Daniel Golle <daniel@makrotopia.org>
Acked-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-1-04a0c5cdda52@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-15 11:06:32 +02:00
Ninad Naik
9757300d27 pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets
SA8775 and newer target have added support for an increased number of
interrupt targets. To implement this change, the intr_target field, which
is used to configure the interrupt target in the interrupt configuration
register is increased from 3 bits to 4 bits.

In accordance to these updates, a new intr_target_width member is
introduced in msm_pingroup structure. This member stores the value of
width of intr_target field in the interrupt configuration register. This
value is used to dynamically calculate and generate mask for setting the
intr_target field. By default, this mask is set to 3 bit wide, to ensure
backward compatibility with the older targets.

Fixes: 4b6b185599 ("pinctrl: qcom: add the tlmm driver sa8775p platforms")
Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride
Signed-off-by: Ninad Naik <quic_ninanaik@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230809100634.3961-1-quic_ninanaik@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10 10:48:15 +02:00
Florian Fainelli
c9b2572f48 pinctrl: nsp-gpio: Silence probe deferral messages
We can have gpiochip_add_data() return -EPROBE_DEFER which will make
us produce the "unable to add GPIO chip" message which is confusing.
Use dev_err_probe() to silence probe deferral messages.

Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230808180733.2081353-3-florian.fainelli@broadcom.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10 10:41:20 +02:00
Florian Fainelli
d2606a6365 pinctrl: iproc-gpio: Silence probe deferral messages
We can have gpiochip_add_data() return -EPROBE_DEFER which will make us
produce the "unable to add GPIO chip" message which is confusing. Use
dev_err_probe() to silence probe deferral messages.

Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230808180733.2081353-2-florian.fainelli@broadcom.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10 10:41:20 +02:00
Tony Lindgren
0cec950d3f pinctrl: single: Add compatible for ti,am654-padconf
Use the "ti,am654-padconf" compatible to enable the use of wake-up enable
and event bits on K3 SOCs that support the daisychain feature

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20230808102207.130177-3-d-gole@ti.com
[Alphabetized the compatible list]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10 10:39:17 +02:00
Valentin Caron
32c170ff15 pinctrl: stm32: set default gpio line names using pin names
Add stm32_pctrl_get_desc_pin_from_gpio function to find a stm32 pin
descriptor which is matching with a gpio.
Most of the time pin number is equal to pin index in array. So the first
part of the function is useful to speed up.

And during gpio bank register, we set default gpio names with pin names.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@foss.st.com>
Link: https://lore.kernel.org/r/20230620104349.834687-1-valentin.caron@foss.st.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-08-10 10:12:39 +02:00