linux-stable/arch/riscv
Haorong Lu 79fc40a29d riscv: signal: handle syscall restart before get_signal
commit ce4f78f1b5 upstream.

In the current riscv implementation, blocking syscalls like read() may
not correctly restart after being interrupted by ptrace. This problem
arises when the syscall restart process in arch_do_signal_or_restart()
is bypassed due to changes to the regs->cause register, such as an
ebreak instruction.

Steps to reproduce:
1. Interrupt the tracee process with PTRACE_SEIZE & PTRACE_INTERRUPT.
2. Backup original registers and instruction at new_pc.
3. Change pc to new_pc, and inject an instruction (like ebreak) to this
   address.
4. Resume with PTRACE_CONT and wait for the process to stop again after
   executing ebreak.
5. Restore original registers and instructions, and detach from the
   tracee process.
6. Now the read() syscall in tracee will return -1 with errno set to
   ERESTARTSYS.

Specifically, during an interrupt, the regs->cause changes from
EXC_SYSCALL to EXC_BREAKPOINT due to the injected ebreak, which is
inaccessible via ptrace so we cannot restore it. This alteration breaks
the syscall restart condition and ends the read() syscall with an
ERESTARTSYS error. According to include/linux/errno.h, it should never
be seen by user programs. X86 can avoid this issue as it checks the
syscall condition using a register (orig_ax) exposed to user space.
Arm64 handles syscall restart before calling get_signal, where it could
be paused and inspected by ptrace/debugger.

This patch adjusts the riscv implementation to arm64 style, which also
checks syscall using a kernel register (syscallno). It ensures the
syscall restart process is not bypassed when changes to the cause
register occur, providing more consistent behavior across various
architectures.

For a simplified reproduction program, feel free to visit:
https://github.com/ancientmodern/riscv-ptrace-bug-demo.

Signed-off-by: Haorong Lu <ancientmodern4@gmail.com>
Link: https://lore.kernel.org/r/20230803224458.4156006-1-ancientmodern4@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Cc: Conor Dooley <conor@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-06-16 13:41:31 +02:00
..
boot riscv: dts: sifive: add missing #interrupt-cells to pmic 2024-03-26 18:20:25 -04:00
configs riscv: enable CD-ROM file systems in defconfig 2022-08-25 17:01:09 -07:00
errata RISC-V: fix taking the text_mutex twice during sifive errata patching 2023-05-17 11:53:41 +02:00
include riscv: Fix TASK_SIZE on 64-bit NOMMU 2024-05-02 16:29:31 +02:00
kernel riscv: signal: handle syscall restart before get_signal 2024-06-16 13:41:31 +02:00
kvm RISC-V: Align SBI probe implementation with spec 2023-05-11 23:03:04 +09:00
lib riscv: uaccess: Return the number of bytes effectively not copied 2023-08-23 17:52:38 +02:00
mm riscv: Fix wrong usage of lm_alias() when splitting a huge linear mapping 2024-01-25 15:27:52 -08:00
net riscv, bpf: make some atomic operations fully ordered 2024-06-12 11:03:19 +02:00
purgatory riscv/purgatory: remove PGO flags 2023-06-21 16:00:55 +02:00
Kbuild riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild 2022-06-01 22:26:32 -07:00
Kconfig riscv: Fix build errors using binutils2.37 toolchains 2023-08-30 16:11:08 +02:00
Kconfig.debug
Kconfig.erratas riscv: make t-head erratas depend on MMU 2022-09-17 01:48:22 -07:00
Kconfig.socs riscv: Kconfig: Add select ARM_AMBA to SOC_STARFIVE 2023-12-13 18:39:29 +01:00
Makefile riscv: Handle zicsr/zifencei issues between clang and binutils 2023-03-30 12:49:28 +02:00